9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
93 lines
4.1 KiB
LLVM
93 lines
4.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
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declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
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declare { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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; FUNC-LABEL: {{^}}ssubo_i64_zext:
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define amdgpu_kernel void @ssubo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b) nounwind {
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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%ext = zext i1 %carry to i64
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%add2 = add i64 %val, %ext
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store i64 %add2, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_ssubo_i32:
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define amdgpu_kernel void @s_ssubo_i32(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i32 %a, i32 %b) nounwind {
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%ssub = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %ssub, 0
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%carry = extractvalue { i32, i1 } %ssub, 1
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store i32 %val, ptr addrspace(1) %out, align 4
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store i1 %carry, ptr addrspace(1) %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_i32:
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define amdgpu_kernel void @v_ssubo_i32(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
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%a = load i32, ptr addrspace(1) %aptr, align 4
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%b = load i32, ptr addrspace(1) %bptr, align 4
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%ssub = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %ssub, 0
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%carry = extractvalue { i32, i1 } %ssub, 1
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store i32 %val, ptr addrspace(1) %out, align 4
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store i1 %carry, ptr addrspace(1) %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_ssubo_i64:
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; GCN: s_sub_u32
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; GCN: s_subb_u32
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define amdgpu_kernel void @s_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) nounwind {
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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store i64 %val, ptr addrspace(1) %out, align 8
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store i1 %carry, ptr addrspace(1) %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
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%a = load i64, ptr addrspace(1) %aptr, align 4
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%b = load i64, ptr addrspace(1) %bptr, align 4
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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store i64 %val, ptr addrspace(1) %out, align 8
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store i1 %carry, ptr addrspace(1) %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_v2i32:
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_sub_{{[iu]}}32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_sub_{{[iu]}}32
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define amdgpu_kernel void @v_ssubo_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
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%a = load <2 x i32>, ptr addrspace(1) %aptr, align 4
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%b = load <2 x i32>, ptr addrspace(1) %bptr, align 4
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%sadd = call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind
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%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
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%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
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store <2 x i32> %val, ptr addrspace(1) %out, align 4
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%carry.ext = zext <2 x i1> %carry to <2 x i32>
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store <2 x i32> %carry.ext, ptr addrspace(1) %carryout
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ret void
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}
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