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clang-p2996/llvm/test/CodeGen/AMDGPU/store-local.ll
Fangrui Song 9e9907f1cf [AMDGPU,test] Change llc -march= to -mtriple= (#75982) 
Similar to 806761a762.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00

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; RUN: llc -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,VI,FUNC %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefixes=CM,FUNC %s
; FUNC-LABEL: {{^}}store_local_i1:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_BYTE_WRITE
; CM: LDS_BYTE_WRITE
; GCN: ds_write_b8
define amdgpu_kernel void @store_local_i1(ptr addrspace(3) %out) {
entry:
store i1 true, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_i8:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_BYTE_WRITE
; CM: LDS_BYTE_WRITE
; GCN: ds_write_b8
define amdgpu_kernel void @store_local_i8(ptr addrspace(3) %out, i8 %in) {
store i8 %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_i16:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_SHORT_WRITE
; CM: LDS_SHORT_WRITE
; GCN: ds_write_b16
define amdgpu_kernel void @store_local_i16(ptr addrspace(3) %out, i16 %in) {
store i16 %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_v2i16:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_WRITE
; CM: LDS_WRITE
; GCN: ds_write_b32
define amdgpu_kernel void @store_local_v2i16(ptr addrspace(3) %out, <2 x i16> %in) {
entry:
store <2 x i16> %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_v4i8:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_WRITE
; CM: LDS_WRITE
; GCN: ds_write_b32
define amdgpu_kernel void @store_local_v4i8(ptr addrspace(3) %out, <4 x i8> %in) {
entry:
store <4 x i8> %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_v4i8_unaligned:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_BYTE_WRITE
; EG: LDS_BYTE_WRITE
; EG: LDS_BYTE_WRITE
; EG: LDS_BYTE_WRITE
; EG-NOT: LDS_WRITE
; CM: LDS_BYTE_WRITE
; CM: LDS_BYTE_WRITE
; CM: LDS_BYTE_WRITE
; CM: LDS_BYTE_WRITE
; CM-NOT: LDS_WRITE
; GCN: ds_write_b8
; GCN: ds_write_b8
; GCN: ds_write_b8
; GCN: ds_write_b8
define amdgpu_kernel void @store_local_v4i8_unaligned(ptr addrspace(3) %out, <4 x i8> %in) {
entry:
store <4 x i8> %in, ptr addrspace(3) %out, align 1
ret void
}
; FUNC-LABEL: {{^}}store_local_v4i8_halfaligned:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_SHORT_WRITE
; EG: LDS_SHORT_WRITE
; EG-NOT: LDS_WRITE
; CM: LDS_SHORT_WRITE
; CM: LDS_SHORT_WRITE
; CM-NOT: LDS_WRITE
; GCN: ds_write_b16
; GCN: ds_write_b16
define amdgpu_kernel void @store_local_v4i8_halfaligned(ptr addrspace(3) %out, <4 x i8> %in) {
entry:
store <4 x i8> %in, ptr addrspace(3) %out, align 2
ret void
}
; FUNC-LABEL: {{^}}store_local_v2i32:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_WRITE
; EG: LDS_WRITE
; EG-NOT: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; CM-NOT: LDS_WRITE
; GCN: ds_write_b64
define amdgpu_kernel void @store_local_v2i32(ptr addrspace(3) %out, <2 x i32> %in) {
entry:
store <2 x i32> %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_v4i32:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_WRITE
; EG: LDS_WRITE
; EG: LDS_WRITE
; EG: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; SI: ds_write2_b32
; VI: ds_write_b128
; GFX9: ds_write_b128
define amdgpu_kernel void @store_local_v4i32(ptr addrspace(3) %out, <4 x i32> %in) {
entry:
store <4 x i32> %in, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_v4i32_align4:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_WRITE
; EG: LDS_WRITE
; EG: LDS_WRITE
; EG: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; CM: LDS_WRITE
; GCN: ds_write2_b32
; GCN: ds_write2_b32
define amdgpu_kernel void @store_local_v4i32_align4(ptr addrspace(3) %out, <4 x i32> %in) {
entry:
store <4 x i32> %in, ptr addrspace(3) %out, align 4
ret void
}
; FUNC-LABEL: {{^}}store_local_i64_i8:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_BYTE_WRITE
; GCN: ds_write_b8
define amdgpu_kernel void @store_local_i64_i8(ptr addrspace(3) %out, i64 %in) {
entry:
%0 = trunc i64 %in to i8
store i8 %0, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}store_local_i64_i16:
; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0
; EG: LDS_SHORT_WRITE
; GCN: ds_write_b16
define amdgpu_kernel void @store_local_i64_i16(ptr addrspace(3) %out, i64 %in) {
entry:
%0 = trunc i64 %in to i16
store i16 %0, ptr addrspace(3) %out
ret void
}
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