b6b703b2df
SIMachineFunctionInfo has a scan of the function body for inline asm
which may use AGPRs, or callees in SIMachineFunctionInfo. Move this
into the attributor, so it actually works interprocedurally.
Could probably avoid most of the test churn if this bothered to avoid
adding this on subtargets without AGPRs. We should also probably
try to delete the MIR scan in usesAGPRs but it seems to be trickier
to eliminate.
108 lines
4.9 KiB
LLVM
108 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd- -passes=amdgpu-attributor %s | FileCheck %s
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; Test to ensure recursive functions exhibit proper behaviour
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; Test to generate fibonacci numbers
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define i32 @fib(i32 %n) #0 {
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; CHECK-LABEL: define {{[^@]+}}@fib
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; CHECK-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[N]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[CONT1:%.*]]
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; CHECK: cont1:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[N]], 1
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; CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
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; CHECK: cont2:
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; CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
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; CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib(i32 [[NM1]])
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; CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
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; CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib(i32 [[NM2]])
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; CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
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; CHECK-NEXT: ret i32 [[RETVAL]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 1
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;
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%cmp1 = icmp eq i32 %n, 0
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br i1 %cmp1, label %exit, label %cont1
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cont1:
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%cmp2 = icmp eq i32 %n, 1
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br i1 %cmp2, label %exit, label %cont2
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cont2:
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%nm1 = sub i32 %n, 1
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%fibm1 = call i32 @fib(i32 %nm1)
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%nm2 = sub i32 %n, 2
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%fibm2 = call i32 @fib(i32 %nm2)
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%retval = add i32 %fibm1, %fibm2
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ret i32 %retval
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exit:
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ret i32 1
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}
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define internal i32 @fib_internal(i32 %n) #0 {
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; CHECK-LABEL: define {{[^@]+}}@fib_internal
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; CHECK-SAME: (i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[N]], 0
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; CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[CONT1:%.*]]
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; CHECK: cont1:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[N]], 1
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; CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
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; CHECK: cont2:
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; CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
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; CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib_internal(i32 [[NM1]])
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; CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
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; CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib_internal(i32 [[NM2]])
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; CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
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; CHECK-NEXT: ret i32 [[RETVAL]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 1
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;
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%cmp1 = icmp eq i32 %n, 0
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br i1 %cmp1, label %exit, label %cont1
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cont1:
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%cmp2 = icmp eq i32 %n, 1
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br i1 %cmp2, label %exit, label %cont2
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cont2:
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%nm1 = sub i32 %n, 1
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%fibm1 = call i32 @fib_internal(i32 %nm1)
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%nm2 = sub i32 %n, 2
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%fibm2 = call i32 @fib_internal(i32 %nm2)
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%retval = add i32 %fibm1, %fibm2
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ret i32 %retval
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exit:
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ret i32 1
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}
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define amdgpu_kernel void @kernel(ptr addrspace(1) %m) #1 {
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; CHECK-LABEL: define {{[^@]+}}@kernel
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; CHECK-SAME: (ptr addrspace(1) [[M:%.*]]) #[[ATTR2:[0-9]+]] {
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; CHECK-NEXT: [[R:%.*]] = call i32 @fib(i32 5)
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; CHECK-NEXT: [[R2:%.*]] = call i32 @fib_internal(i32 5)
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; CHECK-NEXT: store i32 [[R]], ptr addrspace(1) [[M]], align 4
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; CHECK-NEXT: store i32 [[R2]], ptr addrspace(1) [[M]], align 4
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; CHECK-NEXT: ret void
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;
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%r = call i32 @fib(i32 5)
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%r2 = call i32 @fib_internal(i32 5)
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store i32 %r, ptr addrspace(1) %m
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store i32 %r2, ptr addrspace(1) %m
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ret void
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}
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; nounwind and readnone are added to match attributor results.
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attributes #0 = { nounwind readnone }
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attributes #1 = { "uniform-work-group-size"="true" }
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;.
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; CHECK: attributes #[[ATTR0]] = { nounwind memory(none) "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR1]] = { nounwind memory(none) "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="true" }
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; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="true" }
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;.
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