The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31) as artificial regs, similar to how X86 has done it. And emit store /reload instructions for the required halves. PR : https://github.com/llvm/llvm-project/issues/57307 Reviewed By: jhibbits Differential Revision: https://reviews.llvm.org/D152437
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3.0 KiB