60ea6f35a2
Armv8.1-M can be configured to support the integer subset of the MVE vector instructions, and no floating point. In that situation, the FP and vector registers still exist, and so do the load, store and move instructions that transfer data in and out of them. So there's no reason the hard floating point ABI can't be supported, and you might reasonably want to use it, for the sake of intrinsics-based code passing explicit MVE vector types between functions. But the selection of the hard float ABI in the backend was gated on Subtarget->hasVFP2Base(), which is false in the case of integer MVE and no FP. As a result, you'd silently get the soft float ABI even if you deliberately tried to select it, e.g. with clang options such as --target=arm-none-eabi -mfloat-abi=hard -march=armv8.1m.main+nofp+mve The hard float ABI should have been gated on the weaker condition Subtarget->hasFPRegs(), because the only requirement for being able to pass arguments in the FP registers is that the registers themselves should exist. I haven't added a new test, because changing the existing CodeGen/Thumb2/float-ops.ll test seemed sufficient. But I've added a comment explaining why the results are expected to be what they are. Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D142703
312 lines
7.2 KiB
LLVM
312 lines
7.2 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE -check-prefix=NOREGS
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VFP4-ALL
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=FP-ARMv8
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP4-ALL -check-prefix=VFP4-DP
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; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabihf -mattr=+mve | FileCheck %s -check-prefix=CHECK -check-prefix=NONE -check-prefix=ONLYREGS
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define float @add_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: add_f:
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; NONE: {{b|bl}} __aeabi_fadd
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; HARD: vadd.f32 s0, s0, s1
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%0 = fadd float %a, %b
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ret float %0
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}
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define double @add_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: add_d:
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; NONE: {{b|bl}} __aeabi_dadd
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; SP: {{b|bl}} __aeabi_dadd
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; DP: vadd.f64 d0, d0, d1
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%0 = fadd double %a, %b
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ret double %0
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}
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define float @sub_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: sub_f:
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; NONE: {{b|bl}} __aeabi_fsub
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; HARD: vsub.f32 s
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%0 = fsub float %a, %b
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ret float %0
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}
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define double @sub_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: sub_d:
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; NONE: {{b|bl}} __aeabi_dsub
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; SP: {{b|bl}} __aeabi_dsub
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; DP: vsub.f64 d0, d0, d1
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%0 = fsub double %a, %b
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ret double %0
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}
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define float @mul_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: mul_f:
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; NONE: {{b|bl}} __aeabi_fmul
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; HARD: vmul.f32 s
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%0 = fmul float %a, %b
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ret float %0
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}
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define double @mul_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: mul_d:
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; NONE: {{b|bl}} __aeabi_dmul
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; SP: {{b|bl}} __aeabi_dmul
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; DP: vmul.f64 d0, d0, d1
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%0 = fmul double %a, %b
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ret double %0
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}
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define float @div_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: div_f:
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; NONE: {{b|bl}} __aeabi_fdiv
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; HARD: vdiv.f32 s
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%0 = fdiv float %a, %b
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ret float %0
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}
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define double @div_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: div_d:
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; NONE: {{b|bl}} __aeabi_ddiv
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; SP: {{b|bl}} __aeabi_ddiv
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; DP: vdiv.f64 d0, d0, d1
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%0 = fdiv double %a, %b
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ret double %0
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}
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define float @rem_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: rem_f:
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; NONE: {{b|bl}} fmodf
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; HARD: b fmodf
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%0 = frem float %a, %b
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ret float %0
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}
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define double @rem_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: rem_d:
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; NONE: {{b|bl}} fmod
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; HARD: b fmod
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%0 = frem double %a, %b
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ret double %0
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}
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; In the ONLYREGS case (where we have integer MVE but no floating
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; point), we still expect the hard float ABI, because we asked for it
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; in the triple, and since the FP registers exist, it's possible to
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; use them to pass arguments. So the generated code should load the
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; return value into s0, not r0. Similarly for the other load and store
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; tests.
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define float @load_f(ptr %a) {
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entry:
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; CHECK-LABEL: load_f:
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; NOREGS: ldr r0, [r0]
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; ONLYREGS: vldr s0, [r0]
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; HARD: vldr s0, [r0]
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%0 = load float, ptr %a, align 4
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ret float %0
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}
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define double @load_d(ptr %a) {
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entry:
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; CHECK-LABEL: load_d:
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; NOREGS: ldm r0, {r0, r1}
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; ONLYREGS: vldr d0, [r0]
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; HARD: vldr d0, [r0]
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%0 = load double, ptr %a, align 8
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ret double %0
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}
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define void @store_f(ptr %a, float %b) {
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entry:
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; CHECK-LABEL: store_f:
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; NOREGS: str r1, [r0]
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; ONLYREGS: vstr s0, [r0]
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; HARD: vstr s0, [r0]
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store float %b, ptr %a, align 4
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ret void
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}
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define void @store_d(ptr %a, double %b) {
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entry:
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; CHECK-LABEL: store_d:
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; NOREGS: strd r2, r3, [r0]
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; ONLYREGS: vstr d0, [r0]
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; HARD: vstr d0, [r0]
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store double %b, ptr %a, align 8
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ret void
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}
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define double @f_to_d(float %a) {
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; CHECK-LABEL: f_to_d:
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; NONE: bl __aeabi_f2d
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; SP: bl __aeabi_f2d
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; DP: vcvt.f64.f32 d0, s0
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%1 = fpext float %a to double
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ret double %1
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}
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define float @d_to_f(double %a) {
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; CHECK-LABEL: d_to_f:
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; NONE: bl __aeabi_d2f
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; SP: bl __aeabi_d2f
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; DP: vcvt.f32.f64 s0, d0
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%1 = fptrunc double %a to float
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ret float %1
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}
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define i32 @f_to_si(float %a) {
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; CHECK-LABEL: f_to_si:
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; NONE: bl __aeabi_f2iz
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; HARD: vcvt.s32.f32 s0, s0
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; HARD: vmov r0, s0
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define i32 @d_to_si(double %a) {
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; CHECK-LABEL: d_to_si:
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; NONE: bl __aeabi_d2iz
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; SP: vmov r0, r1, d0
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; SP: bl __aeabi_d2iz
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; DP: vcvt.s32.f64 s0, d0
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; DP: vmov r0, s0
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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define i32 @f_to_ui(float %a) {
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; CHECK-LABEL: f_to_ui:
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; NONE: bl __aeabi_f2uiz
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; HARD: vcvt.u32.f32 s0, s0
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; HARD: vmov r0, s0
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define i32 @d_to_ui(double %a) {
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; CHECK-LABEL: d_to_ui:
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; NONE: bl __aeabi_d2uiz
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; SP: vmov r0, r1, d0
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; SP: bl __aeabi_d2uiz
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; DP: vcvt.u32.f64 s0, d0
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; DP: vmov r0, s0
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define float @si_to_f(i32 %a) {
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; CHECK-LABEL: si_to_f:
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; NONE: bl __aeabi_i2f
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; HARD: vcvt.f32.s32 s0, s0
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%1 = sitofp i32 %a to float
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ret float %1
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}
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define double @si_to_d(i32 %a) {
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; CHECK-LABEL: si_to_d:
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; NONE: bl __aeabi_i2d
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; SP: bl __aeabi_i2d
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; DP: vcvt.f64.s32 d0, s0
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%1 = sitofp i32 %a to double
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ret double %1
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}
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define float @ui_to_f(i32 %a) {
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; CHECK-LABEL: ui_to_f:
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; NONE: bl __aeabi_ui2f
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; HARD: vcvt.f32.u32 s0, s0
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define double @ui_to_d(i32 %a) {
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; CHECK-LABEL: ui_to_d:
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; NONE: bl __aeabi_ui2d
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; SP: bl __aeabi_ui2d
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; DP: vcvt.f64.u32 d0, s0
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define float @bitcast_i_to_f(i32 %a) {
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; CHECK-LABEL: bitcast_i_to_f:
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; NOREGS-NOT: mov
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; ONLYREGS: vmov s0, r0
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; HARD: vmov s0, r0
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%1 = bitcast i32 %a to float
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ret float %1
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}
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define double @bitcast_i_to_d(i64 %a) {
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; CHECK-LABEL: bitcast_i_to_d:
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; NOREGS-NOT: mov
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; ONLYREGS: vmov d0, r0, r1
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; HARD: vmov d0, r0, r1
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%1 = bitcast i64 %a to double
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ret double %1
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}
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define i32 @bitcast_f_to_i(float %a) {
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; CHECK-LABEL: bitcast_f_to_i:
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; NOREGS-NOT: mov
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; ONLYREGS: vmov r0, s0
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; HARD: vmov r0, s0
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%1 = bitcast float %a to i32
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ret i32 %1
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}
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define i64 @bitcast_d_to_i(double %a) {
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; CHECK-LABEL: bitcast_d_to_i:
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; NOREGS-NOT: mov
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; ONLYREGS: vmov r0, r1, d0
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; HARD: vmov r0, r1, d0
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%1 = bitcast double %a to i64
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ret i64 %1
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}
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define float @select_f(float %a, float %b, i1 %c) {
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; CHECK-LABEL: select_f:
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; NOREGS: lsls r2, r2, #31
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; NOREGS: moveq r0, r1
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; ONLYREGS: lsls r0, r0, #31
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; ONLYREGS: vmovne.f32 s1, s0
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; HARD: lsls r0, r0, #31
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; VFP4-ALL: vmovne.f32 s1, s0
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; VFP4-ALL: vmov.f32 s0, s1
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; FP-ARMv8: vseleq.f32 s0, s1, s0
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%1 = select i1 %c, float %a, float %b
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ret float %1
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}
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define double @select_d(double %a, double %b, i1 %c) {
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; CHECK-LABEL: select_d:
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; NOREGS: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]
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; NOREGS: ands [[REG]], [[REG]], #1
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; ONLYREGS: ands r0, r0, #1
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; NOREGS-DAG: moveq r0, r2
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; NOREGS-DAG: moveq r1, r3
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; ONLYREGS-DAG: csel r0, r0, r2
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; ONLYREGS-DAG: csel r1, r1, r3
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; SP: ands r0, r0, #1
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; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0
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; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1
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; SP: itt ne
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; SP-DAG: movne [[BLO]], [[ALO]]
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; SP-DAG: movne [[BHI]], [[AHI]]
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; SP: vmov d0, [[BLO]], [[BHI]]
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; DP: lsls r0, r0, #31
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; VFP4-DP: vmovne.f64 d1, d0
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; VFP4-DP: vmov.f64 d0, d1
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; FP-ARMV8: vseleq.f64 d0, d1, d0
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%1 = select i1 %c, double %a, double %b
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ret double %1
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}
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