cbdccb30c2
If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed. The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch. Differential Revision: https://reviews.llvm.org/D156491
225 lines
7.7 KiB
LLVM
225 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-linux < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=i386-unknown-linux < %s | FileCheck %s --check-prefix=CHECK-32BIT
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; Check CSR split can work properly for tests below.
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@a = common dso_local local_unnamed_addr global i32 0, align 4
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define dso_local signext i32 @test1(ptr %b) local_unnamed_addr {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movslq a(%rip), %rax
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; CHECK-NEXT: cmpq %rdi, %rax
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_2: # %if.then
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: callq callVoid@PLT
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; CHECK-NEXT: movq %rbx, %rdi
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: jmp callNonVoid@PLT # TAILCALL
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;
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; CHECK-32BIT-LABEL: test1:
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; CHECK-32BIT: # %bb.0: # %entry
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; CHECK-32BIT-NEXT: subl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 16
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; CHECK-32BIT-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-32BIT-NEXT: cmpl %eax, a
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; CHECK-32BIT-NEXT: je .LBB0_2
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; CHECK-32BIT-NEXT: # %bb.1: # %if.end
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; CHECK-32BIT-NEXT: addl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 4
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; CHECK-32BIT-NEXT: retl
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; CHECK-32BIT-NEXT: .LBB0_2: # %if.then
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 16
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; CHECK-32BIT-NEXT: calll callVoid@PLT
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; CHECK-32BIT-NEXT: addl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 4
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; CHECK-32BIT-NEXT: jmp callNonVoid@PLT # TAILCALL
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entry:
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%0 = load i32, ptr @a, align 4, !tbaa !2
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%conv = sext i32 %0 to i64
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%1 = inttoptr i64 %conv to ptr
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%cmp = icmp eq ptr %1, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = tail call signext i32 @callVoid()
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%call2 = tail call signext i32 @callNonVoid(ptr %b)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%retval.0 = phi i32 [ %call2, %if.then ], [ undef, %entry ]
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ret i32 %retval.0
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}
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declare signext i32 @callVoid(...) local_unnamed_addr
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declare signext i32 @callNonVoid(ptr) local_unnamed_addr
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define dso_local signext i32 @test2(ptr %p1) local_unnamed_addr {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: je .LBB1_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movslq a(%rip), %rax
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; CHECK-NEXT: cmpq %rdi, %rax
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; CHECK-NEXT: je .LBB1_3
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; CHECK-NEXT: .LBB1_2: # %return
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_3: # %if.then2
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: callq callVoid@PLT
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; CHECK-NEXT: movq %rbx, %rdi
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: jmp callNonVoid@PLT # TAILCALL
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;
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; CHECK-32BIT-LABEL: test2:
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; CHECK-32BIT: # %bb.0: # %entry
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; CHECK-32BIT-NEXT: subl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 16
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; CHECK-32BIT-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-32BIT-NEXT: testl %eax, %eax
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; CHECK-32BIT-NEXT: je .LBB1_2
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; CHECK-32BIT-NEXT: # %bb.1: # %if.end
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; CHECK-32BIT-NEXT: cmpl %eax, a
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; CHECK-32BIT-NEXT: je .LBB1_3
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; CHECK-32BIT-NEXT: .LBB1_2: # %return
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; CHECK-32BIT-NEXT: xorl %eax, %eax
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; CHECK-32BIT-NEXT: addl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 4
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; CHECK-32BIT-NEXT: retl
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; CHECK-32BIT-NEXT: .LBB1_3: # %if.then2
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 16
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; CHECK-32BIT-NEXT: calll callVoid@PLT
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; CHECK-32BIT-NEXT: addl $12, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 4
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; CHECK-32BIT-NEXT: jmp callNonVoid@PLT # TAILCALL
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entry:
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%tobool = icmp eq ptr %p1, null
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br i1 %tobool, label %return, label %if.end
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if.end: ; preds = %entry
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%0 = load i32, ptr @a, align 4, !tbaa !2
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%conv = sext i32 %0 to i64
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%1 = inttoptr i64 %conv to ptr
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%cmp = icmp eq ptr %1, %p1
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br i1 %cmp, label %if.then2, label %return
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if.then2: ; preds = %if.end
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%call = tail call signext i32 @callVoid()
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%call3 = tail call signext i32 @callNonVoid(ptr nonnull %p1)
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br label %return
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return: ; preds = %if.end, %entry, %if.then2
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%retval.0 = phi i32 [ %call3, %if.then2 ], [ 0, %entry ], [ 0, %if.end ]
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ret i32 %retval.0
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}
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define dso_local ptr @test3(ptr nocapture %p1, i8 zeroext %p2) local_unnamed_addr {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset %rbx, -24
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; CHECK-NEXT: .cfi_offset %r14, -16
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; CHECK-NEXT: movq (%rdi), %rbx
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; CHECK-NEXT: testq %rbx, %rbx
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; CHECK-NEXT: je .LBB2_2
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; CHECK-NEXT: # %bb.1: # %land.rhs
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; CHECK-NEXT: movq %rdi, %r14
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; CHECK-NEXT: movzbl %sil, %esi
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; CHECK-NEXT: movq %rbx, %rdi
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; CHECK-NEXT: callq bar@PLT
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; CHECK-NEXT: movq %rax, (%r14)
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; CHECK-NEXT: .LBB2_2: # %land.end
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; CHECK-NEXT: movq %rbx, %rax
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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;
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; CHECK-32BIT-LABEL: test3:
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; CHECK-32BIT: # %bb.0: # %entry
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; CHECK-32BIT-NEXT: pushl %edi
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 8
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; CHECK-32BIT-NEXT: pushl %esi
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 12
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; CHECK-32BIT-NEXT: pushl %eax
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 16
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; CHECK-32BIT-NEXT: .cfi_offset %esi, -12
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; CHECK-32BIT-NEXT: .cfi_offset %edi, -8
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; CHECK-32BIT-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK-32BIT-NEXT: movl (%edi), %esi
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; CHECK-32BIT-NEXT: testl %esi, %esi
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; CHECK-32BIT-NEXT: je .LBB2_2
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; CHECK-32BIT-NEXT: # %bb.1: # %land.rhs
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; CHECK-32BIT-NEXT: subl $8, %esp
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; CHECK-32BIT-NEXT: .cfi_adjust_cfa_offset 8
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; CHECK-32BIT-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; CHECK-32BIT-NEXT: pushl %eax
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; CHECK-32BIT-NEXT: .cfi_adjust_cfa_offset 4
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; CHECK-32BIT-NEXT: pushl %esi
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; CHECK-32BIT-NEXT: .cfi_adjust_cfa_offset 4
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; CHECK-32BIT-NEXT: calll bar@PLT
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; CHECK-32BIT-NEXT: addl $16, %esp
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; CHECK-32BIT-NEXT: .cfi_adjust_cfa_offset -16
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; CHECK-32BIT-NEXT: movl %eax, (%edi)
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; CHECK-32BIT-NEXT: .LBB2_2: # %land.end
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; CHECK-32BIT-NEXT: movl %esi, %eax
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; CHECK-32BIT-NEXT: addl $4, %esp
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 12
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; CHECK-32BIT-NEXT: popl %esi
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 8
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; CHECK-32BIT-NEXT: popl %edi
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; CHECK-32BIT-NEXT: .cfi_def_cfa_offset 4
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; CHECK-32BIT-NEXT: retl
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entry:
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%0 = load ptr, ptr %p1, align 8, !tbaa !6
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%tobool = icmp eq ptr %0, null
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br i1 %tobool, label %land.end, label %land.rhs
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land.rhs: ; preds = %entry
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%call = tail call ptr @bar(ptr nonnull %0, i8 zeroext %p2)
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store ptr %call, ptr %p1, align 8, !tbaa !6
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br label %land.end
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land.end: ; preds = %entry, %land.rhs
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ret ptr %0
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}
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declare ptr @bar(ptr, i8 zeroext) local_unnamed_addr
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!llvm.module.flags = !{!0}
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!llvm.ident = !{!1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!"clang version 10.0.0 (trunk 367381) (llvm/trunk 367388)"}
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!2 = !{!3, !3, i64 0}
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!3 = !{!"int", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!7, !7, i64 0}
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!7 = !{!"any pointer", !4, i64 0}
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