d96529af3c
If a shl node leaves the upper half bits zero / undemanded, then see if we can profitably perform this with a half-width shl and a free trunc/zext.
Followup to D146121
Reapplied - moved after the ShrinkDemandedOp call; reuse the existing KnownBits result; ensure that we only attempt this if all the upper bits are demanded; 547dc46122 should address the remaining regressions that were noticed in the previous commit.
Differential Revision: https://reviews.llvm.org/D155472
122 lines
4.8 KiB
LLVM
122 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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define <64 x i4> @pr62653(<64 x i4> %a0) nounwind {
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; CHECK-LABEL: pr62653:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shll $4, %edi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: andl $15, %r10d
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; CHECK-NEXT: orq %rdi, %r10
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shll $8, %edi
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; CHECK-NEXT: orq %r10, %rdi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: andl $15, %r10d
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; CHECK-NEXT: shll $12, %r10d
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; CHECK-NEXT: orq %rdi, %r10
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shll $16, %edi
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; CHECK-NEXT: orq %r10, %rdi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: andl $15, %r10d
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; CHECK-NEXT: shll $20, %r10d
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
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; CHECK-NEXT: andl $15, %r11d
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; CHECK-NEXT: shll $24, %r11d
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; CHECK-NEXT: orq %r10, %r11
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: shll $28, %r10d
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; CHECK-NEXT: orq %r11, %r10
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
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; CHECK-NEXT: andl $15, %r11d
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; CHECK-NEXT: shlq $32, %r11
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; CHECK-NEXT: orq %r10, %r11
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: andl $15, %r10d
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; CHECK-NEXT: shlq $36, %r10
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; CHECK-NEXT: orq %r11, %r10
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; CHECK-NEXT: orq %rdi, %r10
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shlq $40, %rdi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
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; CHECK-NEXT: andl $15, %r11d
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; CHECK-NEXT: shlq $44, %r11
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; CHECK-NEXT: orq %rdi, %r11
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shlq $48, %rdi
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; CHECK-NEXT: orq %r11, %rdi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
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; CHECK-NEXT: andl $15, %r11d
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; CHECK-NEXT: shlq $52, %r11
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; CHECK-NEXT: orq %rdi, %r11
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; CHECK-NEXT: orq %r10, %r11
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; CHECK-NEXT: movq %r11, 8(%rax)
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: andl $15, %edi
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; CHECK-NEXT: shlq $32, %rdi
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; CHECK-NEXT: andl $15, %esi
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: shll $4, %edx
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; CHECK-NEXT: orl %esi, %edx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: shll $8, %ecx
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; CHECK-NEXT: orl %edx, %ecx
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; CHECK-NEXT: andl $15, %r8d
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; CHECK-NEXT: shll $12, %r8d
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; CHECK-NEXT: orl %ecx, %r8d
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; CHECK-NEXT: andl $15, %r9d
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; CHECK-NEXT: shll $16, %r9d
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; CHECK-NEXT: orl %r8d, %r9d
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: shll $20, %ecx
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; CHECK-NEXT: orl %r9d, %ecx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: shll $24, %edx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
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; CHECK-NEXT: shll $28, %esi
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; CHECK-NEXT: orl %edx, %esi
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; CHECK-NEXT: orl %ecx, %esi
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; CHECK-NEXT: orq %rdi, %rsi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: shlq $36, %rcx
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; CHECK-NEXT: orq %rsi, %rcx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: shlq $40, %rdx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: shlq $44, %rcx
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; CHECK-NEXT: orq %rdx, %rcx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: shlq $48, %rdx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
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; CHECK-NEXT: andl $15, %esi
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; CHECK-NEXT: shlq $52, %rsi
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; CHECK-NEXT: orq %rdx, %rsi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: shlq $56, %rdx
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; CHECK-NEXT: orq %rsi, %rdx
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
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; CHECK-NEXT: shlq $60, %rsi
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; CHECK-NEXT: orq %rdx, %rsi
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; CHECK-NEXT: orq %rcx, %rsi
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; CHECK-NEXT: movq %rsi, (%rax)
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; CHECK-NEXT: retq
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%res = shufflevector <64 x i4> %a0, <64 x i4> zeroinitializer, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 64, i32 65, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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ret <64 x i4> %res
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}
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