a20112a74c
This patch adds the assembly/disassembly for the following instructions:
ZERO (ZT0): Zero ZT0.
LDR (ZT0): Load ZT0 register.
STR (ZT0): Store ZT0 register.
MOVT (scalar to ZT0): Move 8 bytes from general-purpose register to ZT0.
(ZT0 to scalar): Move 8 bytes from ZT0 to general-purpose register.
Consecutive:
LUTI2 (single): Lookup table read with 2-bit indexes.
(two registers): Lookup table read with 2-bit indexes.
(four registers): Lookup table read with 2-bit indexes.
LUTI4 (single): Lookup table read with 4-bit indexes.
(two registers): Lookup table read with 4-bit indexes.
(four registers): Lookup table read with 4-bit indexes.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
This patch also adds a new register class and operand for zt0
and a another index operand uimm3s8
Differential Revision: https://reviews.llvm.org/D136088
21 lines
1.0 KiB
ArmAsm
21 lines
1.0 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
|
|
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
|
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
|
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
|
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
|
|
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
|
|
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
|
|
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
|
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
|
|
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
|
|
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
|
|
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
|
|
|
|
|
zero {zt0} // 11000000-01001000-00000000-00000001
|
|
// CHECK-INST: zero { zt0 }
|
|
// CHECK-ENCODING: [0x01,0x00,0x48,0xc0]
|
|
// CHECK-ERROR: instruction requires: sme2
|
|
// CHECK-UNKNOWN: c0480001 <unknown>
|
|
|