[llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#69632)
This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON Instructions:
+ Advanced SIMD two-register miscellaneous:
- F1CVTL, F1CVTL2, F2CVTL, F2CVTL2
- BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
+ Advanced SIMD three-register extension:
- FCVTN, FCVTN2 (FP32 to FP8)
- FCVTN (FP16 to FP8)
+ Advanced SIMD three same:
- FSCALE
* SVE2 Instructions:
+ Downconvert instructions:
- FCVTN_Z2Z_HtoB
- FCVTNB_Z2Z_StoB
- BFCVTN_Z2Z_HtoB
- FCVTNT_Z2Z_StoB
+ Upconvert instructions:
- F1CVT_ZZ, F2CVT_ZZ
- BF1CVT_ZZ, BF2CVT_ZZ
- F1CVTLT_ZZ, F2CVTLT_ZZ
- BF1CVTLT_ZZ, BF2CVTLT_ZZ
* SME2 Instructions:
- F1CVT_2ZZ, F2CVT_2ZZ
- BF1CVT_2ZZ, BF2CVT_2ZZ
- F1CVTL_2ZZ, F2CVTL_2ZZ
- BF1CVTL_2ZZ, BF2CVTL_2ZZ
- FCVT_Z2Z_HtoB, BFCVT_Z2Z_HtoB
- FCVT_Z4Z - FCVTN_Z4Z
- FSCALE_2ZZ, FSCALE_4ZZ
- FSCALE_2Z2Z, FSCALE_4Z4Z
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
78941e1eed