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dda73336ad22bd0b5ecda17040c50fb10fcbe5fb
clang-p2996/llvm/test/tools/llvm-mca/AArch64
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Rin Dobrescu 46246683a6 [AArch64] Update Neoverse V2 FSQRT execution units in schedule model. (#86803)
This patch updates the SVE FSQRT instruction execution units to be able to run on VX0 and VX2.
2024-04-02 10:47:51 +01:00
..
A64FX
[LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437)
2024-03-05 12:34:15 +00:00
Ampere/Ampere1B
[AArch64] Initial Ampere1B scheduling model (#81341)
2024-02-14 15:23:14 +01:00
Cortex
[LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437)
2024-03-05 12:34:15 +00:00
Cyclone
…
Exynos
[CodeGenSchedule] Don't allow invalid ReadAdvances to be formed (#82685)
2024-02-26 18:25:21 -08:00
Falkor
…
HiSilicon
[AArch64] Fix sched model for TSV110 core. (#82343)
2024-02-22 13:01:37 +03:00
Neoverse
[AArch64] Update Neoverse V2 FSQRT execution units in schedule model. (#86803)
2024-04-02 10:47:51 +01:00
lit.local.cfg
…
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