Paul Walker 341d674b6f [LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437) ...

This allows the removal of FFR related psuedo nodes that only existed to
work round machine verifier failures.

2024-03-05 12:34:15 +00:00

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IPC

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A53-carry-over.s

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A53-writeback.s

[AArch64] Fix postinc operands for Cortex-A53 scheduling

2023-10-10 10:14:44 +01:00

A55-add-sequence.s

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A55-all-stats.s

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A55-all-views.s

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A55-basic-instructions.s

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A55-in-order-retire.s

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A55-load-readadv.s

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A55-load-store-alias.s

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A55-load-store-noalias.s

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A55-neon-instructions.s

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A55-out-of-order-retire.s

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A55-store-readadv.s

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A55-writeback.s

[AArch64] Fix postinc operands for Cortex-A55 scheduling

2023-10-10 12:56:33 +01:00

A57-writeback.s

[AArch64] Fix postinc operands for Cortex-A57 scheduling

2023-10-12 10:05:45 +01:00

A510-basic-instructions.s

[AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)

2024-02-01 13:42:14 +00:00

A510-neon-instructions.s

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A510-sve-instructions.s

[LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437)

2024-03-05 12:34:15 +00:00

A510-writeback.s

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A710-sve-instructions.s

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direct-branch.s

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forwarding-A57.s

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in-order-bottleneck-analysis.s

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shifted-register.s

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X2-sve-instructions.s

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