5578ec32f9
This fixes a regression introduced by a very old commit280ac1fd1d(was llvm-svn 361950). Commit280ac1fd1dredesigned the logic in the LSUnit with the goal of speeding up isReady() queries, and stabilising the LSUnit API (while also making the load store unit more customisable). The concept of MemoryGroup (effectively an alias set) was added by that commit to better describe and track dependencies between memory operations. However, that concept was not just used for alias dependencies, but it was also used for describing memory "order" dependencies (enforced by the memory consistency model). Instructions of a same memory group were considered "equivalent" as in: independent operations that can potentially execute in parallel. The problem was that the cost of a dependency (in terms of number of cycles) should have been different for "order" dependency. Instructions in an order dependency simply have to have to wait until their predecessors are "issued" to an underlying pipeline (rather than having to wait until predecessors have beeng fully executed). For simple "order" dependencies, this was effectively introducing an artificial delay on the "issue" of independent loads and stores. This patch fixes the issue and adds a new test named 'independent-load-stores.s' to a bunch of x86 targets. That test contains the reproducible posted by Fabian Ritter on PR45793. I had to rerun the update-mca-tests script on several files. To avoid expected regressions on some Exynos tests, I have added a -noalias=false flag (to match the old strict behavior on latencies). Some tests for processor Barcelona are improved/fixed by this change and they now show better results. In a few tests we were incorrectly counting the time spent by instructions in a scheduler queue. In one case in particular we now correctly see a store executed out of order. That test was affected by the same underlying issue reported as PR45793. Reviewers: mattd Differential Revision: https://reviews.llvm.org/D79351
143 lines
6.6 KiB
ArmAsm
143 lines
6.6 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M5
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stur d0, [sp, #2]
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stur q0, [sp, #16]
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str b0, [sp], #1
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str q0, [sp], #16
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str h0, [sp, #2]!
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str q0, [sp, #16]!
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str s0, [sp, #4]
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str q0, [sp, #16]
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str d0, [sp, x0, lsl #3]
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str q0, [sp, x0, lsl #4]
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str b0, [sp, x0]
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str q0, [sp, x0]
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str h0, [sp, w0, sxtw #1]
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str q0, [sp, w0, uxtw #4]
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str s0, [sp, w0, sxtw]
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str q0, [sp, w0, uxtw]
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stp d0, d1, [sp], #16
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stp q0, q1, [sp], #32
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stp s0, s1, [sp, #8]!
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stp q0, q1, [sp, #32]!
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stp d0, d1, [sp, #16]
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stp q0, q1, [sp, #32]
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 2200
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# M3-NEXT: Total Cycles: 3203
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# M3-NEXT: Total uOps: 2900
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# M4-NEXT: Total Cycles: 3203
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# M4-NEXT: Total uOps: 3000
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# M5-NEXT: Total Cycles: 2803
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# M5-NEXT: Total uOps: 2500
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# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 0.91
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# M3-NEXT: IPC: 0.69
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# M3-NEXT: Block RThroughput: 22.0
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# M4-NEXT: uOps Per Cycle: 0.94
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# M4-NEXT: IPC: 0.69
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# M4-NEXT: Block RThroughput: 12.5
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# M5-NEXT: uOps Per Cycle: 0.89
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# M5-NEXT: IPC: 0.78
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# M5-NEXT: Block RThroughput: 11.0
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# M3-NEXT: 1 1 1.00 * stur d0, [sp, #2]
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# M3-NEXT: 1 1 1.00 * stur q0, [sp, #16]
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# M3-NEXT: 1 1 1.00 * str b0, [sp], #1
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# M3-NEXT: 1 1 1.00 * str q0, [sp], #16
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# M3-NEXT: 1 1 1.00 * str h0, [sp, #2]!
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# M3-NEXT: 1 1 1.00 * str q0, [sp, #16]!
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# M3-NEXT: 1 1 1.00 * str s0, [sp, #4]
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# M3-NEXT: 1 1 1.00 * str q0, [sp, #16]
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# M3-NEXT: 1 1 1.00 * str d0, [sp, x0, lsl #3]
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# M3-NEXT: 2 3 1.00 * str q0, [sp, x0, lsl #4]
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# M3-NEXT: 1 1 1.00 * str b0, [sp, x0]
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# M3-NEXT: 1 1 1.00 * str q0, [sp, x0]
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# M3-NEXT: 2 3 1.00 * str h0, [sp, w0, sxtw #1]
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# M3-NEXT: 2 3 1.00 * str q0, [sp, w0, uxtw #4]
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# M3-NEXT: 2 3 1.00 * str s0, [sp, w0, sxtw]
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# M3-NEXT: 2 3 1.00 * str q0, [sp, w0, uxtw]
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# M3-NEXT: 1 1 1.00 * stp d0, d1, [sp], #16
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# M3-NEXT: 2 1 1.00 * stp q0, q1, [sp], #32
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# M3-NEXT: 1 1 1.00 * stp s0, s1, [sp, #8]!
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# M3-NEXT: 2 1 1.00 * stp q0, q1, [sp, #32]!
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# M3-NEXT: 1 1 1.00 * stp d0, d1, [sp, #16]
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# M3-NEXT: 1 1 1.00 * stp q0, q1, [sp, #32]
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# M4-NEXT: 1 1 0.50 * stur d0, [sp, #2]
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# M4-NEXT: 1 1 0.50 * stur q0, [sp, #16]
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# M4-NEXT: 1 1 0.50 * str b0, [sp], #1
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# M4-NEXT: 1 1 0.50 * str q0, [sp], #16
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# M4-NEXT: 1 1 0.50 * str h0, [sp, #2]!
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# M4-NEXT: 1 1 0.50 * str q0, [sp, #16]!
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# M4-NEXT: 1 1 0.50 * str s0, [sp, #4]
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# M4-NEXT: 1 1 0.50 * str q0, [sp, #16]
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# M4-NEXT: 1 1 0.50 * str d0, [sp, x0, lsl #3]
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# M4-NEXT: 2 3 0.50 * str q0, [sp, x0, lsl #4]
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# M4-NEXT: 1 1 0.50 * str b0, [sp, x0]
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# M4-NEXT: 1 1 0.50 * str q0, [sp, x0]
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# M4-NEXT: 2 3 0.50 * str h0, [sp, w0, sxtw #1]
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# M4-NEXT: 2 3 0.50 * str q0, [sp, w0, uxtw #4]
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# M4-NEXT: 2 3 0.50 * str s0, [sp, w0, sxtw]
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# M4-NEXT: 2 3 0.50 * str q0, [sp, w0, uxtw]
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# M4-NEXT: 1 1 0.50 * stp d0, d1, [sp], #16
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# M4-NEXT: 2 1 1.00 * stp q0, q1, [sp], #32
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# M4-NEXT: 1 1 0.50 * stp s0, s1, [sp, #8]!
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# M4-NEXT: 2 1 1.00 * stp q0, q1, [sp, #32]!
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# M4-NEXT: 1 1 0.50 * stp d0, d1, [sp, #16]
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# M4-NEXT: 2 1 1.00 * stp q0, q1, [sp, #32]
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# M5-NEXT: 1 1 0.50 * stur d0, [sp, #2]
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# M5-NEXT: 1 1 0.50 * stur q0, [sp, #16]
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# M5-NEXT: 1 1 0.50 * str b0, [sp], #1
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# M5-NEXT: 1 1 0.50 * str q0, [sp], #16
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# M5-NEXT: 1 1 0.50 * str h0, [sp, #2]!
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# M5-NEXT: 1 1 0.50 * str q0, [sp, #16]!
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# M5-NEXT: 1 1 0.50 * str s0, [sp, #4]
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# M5-NEXT: 1 1 0.50 * str q0, [sp, #16]
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# M5-NEXT: 1 1 0.50 * str d0, [sp, x0, lsl #3]
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# M5-NEXT: 2 3 0.50 * str q0, [sp, x0, lsl #4]
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# M5-NEXT: 1 1 0.50 * str b0, [sp, x0]
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# M5-NEXT: 1 1 0.50 * str q0, [sp, x0]
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# M5-NEXT: 1 1 0.50 * str h0, [sp, w0, sxtw #1]
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# M5-NEXT: 2 3 0.50 * str q0, [sp, w0, uxtw #4]
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# M5-NEXT: 1 1 0.50 * str s0, [sp, w0, sxtw]
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# M5-NEXT: 2 3 0.50 * str q0, [sp, w0, uxtw]
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# M5-NEXT: 1 1 0.50 * stp d0, d1, [sp], #16
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# M5-NEXT: 1 1 1.00 * stp q0, q1, [sp], #32
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# M5-NEXT: 1 1 0.50 * stp s0, s1, [sp, #8]!
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# M5-NEXT: 1 1 1.00 * stp q0, q1, [sp, #32]!
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# M5-NEXT: 1 1 0.50 * stp d0, d1, [sp, #16]
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# M5-NEXT: 1 1 1.00 * stp q0, q1, [sp, #32]
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