9f6c00565a
The changeset extends LLVMIR intrinsics with VCIX intrinsics. The VCIX intrinsics allow MLIR users to interact with RISC-V co-processors that are compatible with `XSfvcp` extension Source: https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
89 lines
3.3 KiB
C++
89 lines
3.3 KiB
C++
//===- VCIXToLLVMIRTranslation.cpp - Translate VCIX to LLVM IR ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a translation between the MLIR VCIX dialect and
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// LLVM IR.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.h"
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#include "mlir/Dialect/LLVMIR/VCIXDialect.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/Target/LLVMIR/ModuleTranslation.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/IntrinsicsRISCV.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace mlir;
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using namespace mlir::LLVM;
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using mlir::LLVM::detail::createIntrinsicCall;
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/// Infer XLen type from opcode's type. This is done to avoid passing target
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/// option around.
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static llvm::Type *getXlenType(Attribute opcodeAttr,
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LLVM::ModuleTranslation &moduleTranslation) {
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auto intAttr = opcodeAttr.cast<IntegerAttr>();
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unsigned xlenWidth = intAttr.getType().cast<IntegerType>().getWidth();
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return llvm::Type::getIntNTy(moduleTranslation.getLLVMContext(), xlenWidth);
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}
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/// Return VL for VCIX intrinsic. If vl was previously set, return it,
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/// otherwise construct a constant using fixed vector type.
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static llvm::Value *createVL(llvm::IRBuilderBase &builder, llvm::Value *vl,
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VectorType vtype, llvm::Type *xlen, Location loc,
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LLVM::ModuleTranslation &moduleTranslation) {
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if (vl) {
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assert(vtype.isScalable() &&
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"vl parameter must be set for scalable vectors");
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return builder.CreateZExtOrTrunc(vl, xlen);
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}
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assert(vtype.getRank() == 1 && "Only 1-d fixed vectors are supported");
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return mlir::LLVM::detail::getLLVMConstant(
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xlen,
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IntegerAttr::get(IntegerType::get(&moduleTranslation.getContext(), 64),
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vtype.getShape()[0]),
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loc, moduleTranslation);
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}
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namespace {
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/// Implementation of the dialect interface that converts operations belonging
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/// to the VCIX dialect to LLVM IR.
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class VCIXDialectLLVMIRTranslationInterface
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: public LLVMTranslationDialectInterface {
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public:
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using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
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/// Translates the given operation to LLVM IR using the provided IR builder
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/// and saving the state in `moduleTranslation`.
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LogicalResult
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convertOperation(Operation *op, llvm::IRBuilderBase &builder,
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LLVM::ModuleTranslation &moduleTranslation) const final {
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Operation &opInst = *op;
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#include "mlir/Dialect/LLVMIR/VCIXConversions.inc"
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return failure();
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}
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};
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} // namespace
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void mlir::registerVCIXDialectTranslation(DialectRegistry ®istry) {
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registry.insert<vcix::VCIXDialect>();
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registry.addExtension(+[](MLIRContext *ctx, vcix::VCIXDialect *dialect) {
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dialect->addInterfaces<VCIXDialectLLVMIRTranslationInterface>();
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});
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}
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void mlir::registerVCIXDialectTranslation(MLIRContext &context) {
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DialectRegistry registry;
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registerVCIXDialectTranslation(registry);
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context.appendDialectRegistry(registry);
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}
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