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clang-p2996/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Lukacma d57be195e3 [AArch64] replace SVE intrinsics with no active lanes with zero (#107413) 
This patch extends https://github.com/llvm/llvm-project/pull/73964 and
optimises SVE intrinsics into zero constants when predicate is zero.
2024-09-09 10:28:01 +01:00

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