67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; The goal of the test case is to ensure that the Backend doesn't crash on the stage
|
|
; of type inference. Result SPIR-V is not expected to be valid from the perspective
|
|
; of spirv-val in this case, because there is a difference of accepted return types
|
|
; between atomicrmw and OpAtomicExchange.
|
|
|
|
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
|
|
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
|
|
|
|
; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0
|
|
; CHECK-DAG: %[[#PtrLongTy:]] = OpTypePointer CrossWorkgroup %[[#LongTy]]
|
|
; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0
|
|
; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 1
|
|
; CHECK-DAG: %[[#MemSem:]] = OpConstant %[[#IntTy]] 8
|
|
; CHECK-DAG: %[[#PtrPtrLongTy:]] = OpTypePointer CrossWorkgroup %[[#PtrLongTy]]
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#Arg1:]] = OpFunctionParameter %[[#PtrPtrLongTy]]
|
|
; CHECK: %[[#Arg2:]] = OpFunctionParameter %[[#PtrLongTy]]
|
|
; CHECK: OpAtomicExchange %[[#PtrLongTy]] %[[#Arg1]] %[[#Scope]] %[[#MemSem]] %[[#Arg2]]
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define dso_local spir_func void @test1(ptr addrspace(1) %arg1, ptr addrspace(1) byval(i64) %arg_ptr) {
|
|
entry:
|
|
%r = atomicrmw xchg ptr addrspace(1) %arg1, ptr addrspace(1) %arg_ptr acq_rel
|
|
ret void
|
|
}
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#Arg3:]] = OpFunctionParameter %[[#PtrLongTy]]
|
|
; CHECK: %[[#Arg4:]] = OpFunctionParameter %[[#LongTy]]
|
|
; CHECK: OpAtomicExchange %[[#LongTy]] %[[#Arg3]] %[[#Scope]] %[[#MemSem]] %[[#Arg4]]
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define dso_local spir_func void @test2(ptr addrspace(1) %arg1, i64 %arg_ptr) {
|
|
entry:
|
|
%r = atomicrmw xchg ptr addrspace(1) %arg1, i64 %arg_ptr acq_rel
|
|
ret void
|
|
}
|