67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
128 lines
4.7 KiB
LLVM
128 lines
4.7 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
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; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
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; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
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; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
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; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
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; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
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; CHECK-DAG: OpName [[AND:%.*]] "test_and"
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; CHECK-DAG: OpName [[OR:%.*]] "test_or"
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; CHECK-DAG: OpName [[XOR:%.*]] "test_xor"
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; CHECK-DAG: [[I32Ty:%.*]] = OpTypeInt 32 0
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; CHECK-DAG: [[PtrI32Ty:%.*]] = OpTypePointer Function [[I32Ty]]
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;; Device scope is encoded with constant 1
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; CHECK-DAG: [[SCOPE:%.*]] = OpConstant [[I32Ty]] 1
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;; "sequentially consistent" maps to constant 16
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; CHECK-DAG: [[SEQ:%.*]] = OpConstant [[I32Ty]] 16
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; CHECK: [[ADD]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicIAdd [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_add(i32* %ptr, i32 %val) {
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%r = atomicrmw add i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[SUB]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicISub [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_sub(i32* %ptr, i32 %val) {
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%r = atomicrmw sub i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[MIN]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicSMin [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_min(i32* %ptr, i32 %val) {
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%r = atomicrmw min i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[MAX]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicSMax [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_max(i32* %ptr, i32 %val) {
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%r = atomicrmw max i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[UMIN]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicUMin [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_umin(i32* %ptr, i32 %val) {
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%r = atomicrmw umin i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[UMAX]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicUMax [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_umax(i32* %ptr, i32 %val) {
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%r = atomicrmw umax i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[AND]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicAnd [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_and(i32* %ptr, i32 %val) {
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%r = atomicrmw and i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[OR]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicOr [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_or(i32* %ptr, i32 %val) {
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%r = atomicrmw or i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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; CHECK: [[XOR]] = OpFunction [[I32Ty]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[PtrI32Ty]]
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; CHECK-NEXT: [[B:%.*]] = OpFunctionParameter [[I32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.*]] = OpAtomicXor [[I32Ty]] [[A]] [[SCOPE]] [[SEQ]] [[B]]
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @test_xor(i32* %ptr, i32 %val) {
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%r = atomicrmw xor i32* %ptr, i32 %val seq_cst
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ret i32 %r
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}
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