6c783e19ef
This PR has following changes/fixes to XeGPU definition: - Fix type print format for atomic_rmw - removed 2D support for MaskType - Update LoadNd definition - Add 1D TensorDesc support - Replaced vnni_axis attribute with packed attribute - Update DPAS op definition, limiting A to 2D vector, and B to either 2D/3D vector.
450 lines
15 KiB
C++
450 lines
15 KiB
C++
//===- XeGPUOps.cpp - MLIR XeGPU ops implementation -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/Utils/StaticValueUtils.h"
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#include "mlir/Dialect/XeGPU/IR/XeGPU.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/TypeUtilities.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "xegpu"
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namespace mlir {
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namespace xegpu {
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static void transpose(llvm::ArrayRef<int64_t> trans,
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SmallVector<int64_t> &shape) {
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SmallVector<int64_t> old = shape;
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for (size_t i = 0; i < trans.size(); i++)
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shape[i] = old[trans[i]];
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}
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template <typename T>
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static std::string makeString(T array, bool breakline = false) {
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std::string buf;
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buf.clear();
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llvm::raw_string_ostream os(buf);
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os << "[";
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for (size_t i = 1; i < array.size(); i++) {
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os << array[i - 1] << ", ";
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if (breakline)
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os << "\n\t\t";
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}
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os << array.back() << "]";
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os.flush();
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return buf;
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}
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static SmallVector<int64_t> getShapeOf(Type type) {
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SmallVector<int64_t> shape;
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if (auto ty = llvm::dyn_cast<ShapedType>(type))
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shape = SmallVector<int64_t>(ty.getShape());
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else
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shape.push_back(1);
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return shape;
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}
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static int64_t getRankOf(Value val) {
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auto type = val.getType();
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if (auto ty = llvm::dyn_cast<ShapedType>(type))
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return ty.getRank();
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return 0;
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}
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static bool isReadHintOrNone(const CachePolicyAttr &attr) {
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if (!attr)
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return true;
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auto kind = attr.getValue();
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return kind == CachePolicy::CACHED || kind == CachePolicy::UNCACHED ||
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kind == CachePolicy::STREAMING || kind == CachePolicy::READ_INVALIDATE;
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}
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static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
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if (!attr)
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return true;
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auto kind = attr.getValue();
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return kind == CachePolicy::CACHED || kind == CachePolicy::UNCACHED ||
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kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_CreateNdDescOp
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//===----------------------------------------------------------------------===//
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void CreateNdDescOp::build(OpBuilder &builder, OperationState &state,
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Type tdesc, TypedValue<MemRefType> source,
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llvm::ArrayRef<OpFoldResult> offsets) {
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[[maybe_unused]] auto ty = source.getType();
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assert(ty.hasStaticShape() && offsets.size() == (size_t)ty.getRank());
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llvm::SmallVector<int64_t> staticOffsets;
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llvm::SmallVector<Value> dynamicOffsets;
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dispatchIndexOpFoldResults(offsets, dynamicOffsets, staticOffsets);
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build(builder, state, tdesc, source, dynamicOffsets /* dynamic offsets */,
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ValueRange({}) /* empty dynamic shape */,
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ValueRange({}) /* empty dynamic strides */,
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staticOffsets /* const offsets */, {} /* empty const shape*/,
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{} /* empty const strides*/);
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}
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void CreateNdDescOp::build(OpBuilder &builder, OperationState &state,
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Type tdesc, TypedValue<IntegerType> source,
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llvm::ArrayRef<OpFoldResult> offsets,
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llvm::ArrayRef<OpFoldResult> shape,
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llvm::ArrayRef<OpFoldResult> strides) {
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assert(shape.size() && offsets.size() && strides.size() &&
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shape.size() == strides.size() && shape.size() == offsets.size());
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llvm::SmallVector<int64_t> staticOffsets;
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llvm::SmallVector<int64_t> staticShape;
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llvm::SmallVector<int64_t> staticStrides;
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llvm::SmallVector<Value> dynamicOffsets;
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llvm::SmallVector<Value> dynamicShape;
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llvm::SmallVector<Value> dynamicStrides;
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dispatchIndexOpFoldResults(offsets, dynamicOffsets, staticOffsets);
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dispatchIndexOpFoldResults(shape, dynamicShape, staticShape);
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dispatchIndexOpFoldResults(strides, dynamicStrides, staticStrides);
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auto staticOffsetsAttr = builder.getDenseI64ArrayAttr(staticOffsets);
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auto staticShapeAttr = builder.getDenseI64ArrayAttr(staticShape);
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auto staticStridesAttr = builder.getDenseI64ArrayAttr(staticStrides);
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build(builder, state, tdesc, source, dynamicOffsets, dynamicShape,
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dynamicStrides, staticOffsetsAttr, staticShapeAttr, staticStridesAttr);
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}
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LogicalResult CreateNdDescOp::verify() {
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auto rank = (int64_t)getMixedOffsets().size();
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bool invalidRank = false;
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bool invalidElemTy = false;
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// check source type matches the rank if it is a memref.
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// It also should have the same ElementType as TensorDesc.
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auto memrefTy = dyn_cast<MemRefType>(getSourceType());
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if (memrefTy) {
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invalidRank |= (memrefTy.getRank() != rank);
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invalidElemTy |= memrefTy.getElementType() != getElementType();
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}
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// mismatches among shape, strides, and offsets are
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// already handeled by OffsetSizeAndStrideOpInterface.
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// So they are not check here.
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if (invalidRank)
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return emitOpError(
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"Expecting the rank of shape, strides, offsets, and source (if source "
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"is a memref) should match with each other.");
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// check result TensorDesc rank
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invalidRank = (getType().getRank() > 2 || getType().getRank() > rank);
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if (invalidRank)
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return emitOpError(
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"Expecting the TensorDesc rank is up to 2 and not greater than the "
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"ranks of shape, strides, offsets or the memref source.");
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if (invalidElemTy)
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return emitOpError("TensorDesc should have the same element "
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"type with the source if it is a memref.\n");
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if (getType().getScattered())
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return emitOpError("Expects a non-scattered TensorDesc.\n");
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_PrefetchNdOp
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//===----------------------------------------------------------------------===//
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LogicalResult PrefetchNdOp::verify() {
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auto tdescTy = getTensorDescType();
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if (tdescTy.getScattered())
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return emitOpError("Expects a non-scattered TensorDesc.\n");
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if (!isReadHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isReadHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isReadHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_LoadNdOp
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//===----------------------------------------------------------------------===//
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LogicalResult LoadNdOp::verify() {
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auto tdescTy = getTensorDescType();
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auto valueTy = getType();
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if (tdescTy.getRank() > 2)
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return emitOpError("Expecting a 1D/2D TensorDesc.\n");
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if (tdescTy.getScattered())
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return emitOpError("Expects a non-scattered TensorDesc.\n");
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if (!valueTy)
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return emitOpError("Invalid result, it should be a VectorType.\n");
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if (!isReadHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isReadHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isReadHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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auto array_len = tdescTy.getArrayLength();
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auto tdescShape = getShapeOf(tdescTy);
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auto valueShape = getShapeOf(valueTy);
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if (getTranspose()) {
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auto trans = getTranspose().value();
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// Make sure the transpose value is valid.
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bool valid = std::all_of(trans.begin(), trans.end(), [&](int t) {
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return t >= 0 && t < tdescTy.getRank();
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});
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if (valid)
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transpose(trans, tdescShape);
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else
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emitWarning("Invalid transpose attr. It is ignored.");
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}
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if (getPacked()) {
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if (tdescTy.getRank() == 2) {
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const int axis = 0;
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auto vnni_factor = valueShape.back();
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tdescShape[axis] /= vnni_factor;
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tdescShape.push_back(vnni_factor);
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} else {
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return emitWarning("Invalid Packed Attr. It is ignored (available for 2D "
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"TensorDesc only).");
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}
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}
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if (array_len > 1) {
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auto it = tdescShape.begin();
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tdescShape.insert(it, array_len);
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}
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if (tdescShape != valueShape)
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return emitOpError() << "Result shape doesn't match TensorDesc shape."
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<< "The expected shape is " << makeString(tdescShape)
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<< ". But the given shape is "
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<< makeString(valueShape) << ".\n";
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_StoreNdOp
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//===----------------------------------------------------------------------===//
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LogicalResult StoreNdOp::verify() {
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auto dstTy = getTensorDescType(); // Tile
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auto valTy = getValueType(); // Vector
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if (dstTy.getRank() > 2)
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return emitOpError("Expecting a 1D/2D TensorDesc.\n");
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if (dstTy.getScattered())
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return emitOpError("Expects a non-scattered TensorDesc.\n");
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if (!valTy)
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return emitOpError("Exepcting a VectorType result.\n");
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if (!isWriteHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isWriteHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isWriteHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_UpdateNDOffsetOp
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//===----------------------------------------------------------------------===//
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LogicalResult UpdateNdOffsetOp::verify() {
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auto ty = getTensorDescType();
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if (ty.getScattered())
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return emitOpError("Expects a non-scattered TensorDesc.\n");
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// number of offsets specified must match the rank of the tensor descriptor
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if (ty.getRank() != (int64_t)getNumOffsets()) {
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return emitOpError("Invalid number of offsets.");
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}
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_CreateDescOp
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//===----------------------------------------------------------------------===//
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void CreateDescOp::build(OpBuilder &builder, OperationState &state,
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TensorDescType TensorDesc, Value source,
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llvm::ArrayRef<OpFoldResult> offsets,
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uint32_t chunk_size) {
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llvm::SmallVector<int64_t> staticOffsets;
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llvm::SmallVector<Value> dynamicOffsets;
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dispatchIndexOpFoldResults(offsets, dynamicOffsets, staticOffsets);
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build(builder, state, TensorDesc, source, dynamicOffsets, staticOffsets,
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chunk_size);
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}
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LogicalResult CreateDescOp::verify() {
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auto tdescTy = getTensorDescType();
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auto chunkSize = getChunkSize();
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if (getRankOf(getSource()) > 1)
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return emitOpError(
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"Expecting the source is a 1D memref or pointer (uint64_t).");
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if (!tdescTy.getScattered())
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return emitOpError("Expects a scattered TensorDesc.\n");
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SmallVector<int64_t> shape({(int64_t)getNumOffsets()});
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if (chunkSize != 1)
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shape.push_back(chunkSize);
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auto tdescShape = getShapeOf(tdescTy);
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if (shape != tdescShape)
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return emitOpError("Incorrect TensorDesc shape. ")
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<< "Expected is " << makeString(shape) << "\n";
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_PrefetchOp
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//===----------------------------------------------------------------------===//
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LogicalResult PrefetchOp::verify() {
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auto tdescTy = getTensorDescType();
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if (!tdescTy.getScattered())
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return emitOpError("Expects a scattered TensorDesc.\n");
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if (!isReadHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isReadHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isReadHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_LoadGatherOp
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//===----------------------------------------------------------------------===//
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LogicalResult LoadGatherOp::verify() {
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auto tdescTy = getTensorDescType();
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auto maskTy = getMaskType();
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auto valueTy = getValueType();
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if (!tdescTy.getScattered())
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return emitOpError("Expects a scattered TensorDesc.\n");
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if (!isReadHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isReadHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isReadHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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auto tdescElemTy = tdescTy.getElementType();
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auto valueElemTy = getElementType();
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if (tdescElemTy != valueElemTy)
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return emitOpError(
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"Value should have the same element type as TensorDesc.");
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auto maskShape = getShapeOf(maskTy);
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auto valueShape = getShapeOf(valueTy);
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auto tdescShape = getShapeOf(tdescTy);
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if (tdescShape[0] != maskShape[0])
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return emitOpError("dim-0 of the Mask and TensorDesc should be the same.");
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if (getTransposeAttr()) {
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auto trans = getTranspose().value();
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if (tdescShape.size() < trans.size())
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emitWarning("Invalid transpose attr. It is ignored.");
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else
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transpose(trans, tdescShape);
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}
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if (valueShape != tdescShape)
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return emitOpError("Unexpected result shape")
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<< "(Expected shape: " << makeString(tdescShape)
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<< ", Given shape: " << makeString(valueShape) << ").\n";
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_StoreScatterOp
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//===----------------------------------------------------------------------===//
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LogicalResult StoreScatterOp::verify() {
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auto tdescTy = getTensorDescType();
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if (!tdescTy.getScattered())
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return emitOpError("Expects a scattered TensorDesc.\n");
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if (!isWriteHintOrNone(getL1HintAttr()))
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return emitOpError("invlid l1_hint: ") << getL1HintAttr();
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if (!isWriteHintOrNone(getL2HintAttr()))
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return emitOpError("invlid l2_hint: ") << getL2HintAttr();
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if (!isWriteHintOrNone(getL3HintAttr()))
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return emitOpError("invlid l3_hint: ") << getL3HintAttr();
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auto maskTy = getMaskType();
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auto maskShape = getShapeOf(maskTy);
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auto tdescShape = getShapeOf(tdescTy);
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if (tdescShape[0] != maskShape[0])
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return emitOpError("dim-0 of the Mask and TensorDesc should be the same.");
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return success();
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}
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//===----------------------------------------------------------------------===//
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// XeGPU_DpasOp
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//===----------------------------------------------------------------------===//
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LogicalResult DpasOp::verify() {
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int64_t lhsRank = getLhsType().getRank();
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int64_t rhsRank = getRhsType().getRank();
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if (lhsRank != 2 || (rhsRank != 2 && rhsRank != 3))
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return emitOpError("expecting lhs to be a 2D vector, and rhs to be either "
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"2D or 3D (packed) vector.");
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auto lhsShape = getLhsType().getShape();
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auto rhsShape = getRhsType().getShape();
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auto bK = rhsRank == 3 ? rhsShape[0] * rhsShape[2] : rhsShape[0];
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if (bK != lhsShape[1])
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return emitOpError("K-dimension mismatch.");
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return success();
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}
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} // namespace xegpu
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} // namespace mlir
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#include <mlir/Dialect/XeGPU/IR/XeGPUEnums.cpp.inc>
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#define GET_OP_CLASSES
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#include <mlir/Dialect/XeGPU/IR/XeGPU.cpp.inc>
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