dd1df099ae
Before this patch, the compiler gave a bump to the inline-threshold when the total size of the allocas passed as arguments to the callee was below 256 bytes. This heuristic ignores that some of these allocas could have be removed by SROA if inlining was applied. Ideally, this bonus would be attributed to the threshold once the size of all the allocas that could not be handled by SROA is known: at the end of the InlineCost analysis. However, we may never reach this point if the inline-cost analysis exits early when the inline cost goes over the threshold mid-analysis. This patch proposes: * Attribute the bonus in the inline-threshold when allocas are passed as arguments (regardless of their total size). * Assigns a cost to each alloca proportional to its size, such that the cost of all the allocas cancels the bonus. Potential problems: * This patch assumes that removing alloca instructions with SROA is always profitable. This may not be the case if the total size of the allocas is still too big to be promoted to registers/LDS. * Redundant calls to getTotalAllocaSize * Awkwardly, the threshold attributed contributes to the single-bb and vector bonus. Reviewed By: scchan Differential Revision: https://reviews.llvm.org/D149741
180 lines
8.1 KiB
LLVM
180 lines
8.1 KiB
LLVM
; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s
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; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s
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; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s
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; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s
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; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -amdgpu-inline-max-bb=1 < %s | FileCheck -check-prefixes=GCN,GCN-MAXBB1 %s
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define coldcc float @foo(float %x, float %y) {
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entry:
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%cmp = fcmp ogt float %x, 0.000000e+00
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%div = fdiv float %y, %x
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%mul = fmul float %x, %y
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%cond = select i1 %cmp, float %div, float %mul
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ret float %cond
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}
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define coldcc void @foo_private_ptr(ptr addrspace(5) nocapture %p) {
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entry:
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%tmp1 = load float, ptr addrspace(5) %p, align 4
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%cmp = fcmp ogt float %tmp1, 1.000000e+00
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%div = fdiv float 1.000000e+00, %tmp1
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store float %div, ptr addrspace(5) %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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define coldcc void @foo_private_ptr2(ptr addrspace(5) nocapture %p1, ptr addrspace(5) nocapture %p2) {
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entry:
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call void @forbid_sroa(ptr addrspace(5) %p1)
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call void @forbid_sroa(ptr addrspace(5) %p2)
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%tmp1 = load float, ptr addrspace(5) %p1, align 4
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%cmp = fcmp ogt float %tmp1, 1.000000e+00
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%div = fdiv float 2.000000e+00, %tmp1
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store float %div, ptr addrspace(5) %p2, align 4
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br label %if.end
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if.end:
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ret void
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}
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define float @sin_wrapper(float %x) {
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bb:
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%call = tail call float @_Z3sinf(float %x)
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ret float %call
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}
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define void @foo_noinline(ptr addrspace(5) nocapture %p) #0 {
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entry:
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%tmp1 = load float, ptr addrspace(5) %p, align 4
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%mul = fmul float %tmp1, 2.000000e+00
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store float %mul, ptr addrspace(5) %p, align 4
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ret void
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}
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; GCN: define amdgpu_kernel void @test_inliner(
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; GCN-INL1: %c1 = tail call coldcc float @foo(
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; GCN-INLDEF: %cmp.i = fcmp ogt float %tmp2, 0.000000e+00
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; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c
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; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
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; GCN-MAXBB1: call coldcc void @foo_private_ptr
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; GCN-MAXBB1: call coldcc void @foo_private_ptr2
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; GCN: call void @foo_noinline(
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; GCN: tail call float @_Z3sinf(
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define amdgpu_kernel void @test_inliner(ptr addrspace(1) nocapture %a, i32 %n) {
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entry:
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%pvt_arr = alloca [64 x float], align 4, addrspace(5)
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
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%tmp2 = load float, ptr addrspace(1) %arrayidx, align 4
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%add = add i32 %tid, 1
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%arrayidx2 = getelementptr inbounds float, ptr addrspace(1) %a, i32 %add
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%tmp5 = load float, ptr addrspace(1) %arrayidx2, align 4
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%c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
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%or = or i32 %tid, %n
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%arrayidx5 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
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store float %c1, ptr addrspace(5) %arrayidx5, align 4
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%arrayidx7 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
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call coldcc void @foo_private_ptr(ptr addrspace(5) %arrayidx7)
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%arrayidx8 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 1
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%arrayidx9 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 2
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call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
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call void @foo_noinline(ptr addrspace(5) %arrayidx7)
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%and = and i32 %tid, %n
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%arrayidx11 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %and
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%tmp12 = load float, ptr addrspace(5) %arrayidx11, align 4
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%c2 = call float @sin_wrapper(float %tmp12)
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store float %c2, ptr addrspace(5) %arrayidx7, align 4
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%xor = xor i32 %tid, %n
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%arrayidx16 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %xor
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%tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
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store float %tmp16, ptr addrspace(1) %arrayidx, align 4
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ret void
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}
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; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(
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; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
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; GCN-MAXBB1: call coldcc void @foo_private_ptr2
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define amdgpu_kernel void @test_inliner_multi_pvt_ptr(ptr addrspace(1) nocapture %a, i32 %n, float %v) {
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entry:
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%pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
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%pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
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%or = or i32 %tid, %n
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%arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or
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%arrayidx5 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or
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store float %v, ptr addrspace(5) %arrayidx4, align 4
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store float %v, ptr addrspace(5) %arrayidx5, align 4
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%arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1
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%arrayidx9 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2
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call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
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%xor = xor i32 %tid, %n
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%arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor
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%arrayidx16 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor
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%tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4
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%tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
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%tmp17 = fadd float %tmp15, %tmp16
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store float %tmp17, ptr addrspace(1) %arrayidx, align 4
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ret void
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}
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; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(
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; GCN-INL1: call coldcc void @foo_private_ptr2
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; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
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define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(ptr addrspace(1) nocapture %a, i32 %n, float %v) {
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entry:
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%pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
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%pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
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%or = or i32 %tid, %n
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%arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or
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%arrayidx5 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or
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store float %v, ptr addrspace(5) %arrayidx4, align 4
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store float %v, ptr addrspace(5) %arrayidx5, align 4
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%arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1
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%arrayidx9 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2
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call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
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%xor = xor i32 %tid, %n
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%arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor
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%arrayidx16 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor
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%tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4
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%tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
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%tmp17 = fadd float %tmp15, %tmp16
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store float %tmp17, ptr addrspace(1) %arrayidx, align 4
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ret void
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}
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; GCN: define amdgpu_kernel void @test_inliner_maxbb_singlebb(
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; GCN: tail call float @_Z3sinf
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define amdgpu_kernel void @test_inliner_maxbb_singlebb(ptr addrspace(1) nocapture %a, i32 %n) {
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entry:
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%cmp = icmp eq i32 %n, 1
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br i1 %cmp, label %bb.1, label %bb.2
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br label %bb.1
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bb.1:
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store float 1.0, ptr undef
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br label %bb.2
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bb.2:
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%c = call float @sin_wrapper(float 1.0)
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store float %c, ptr addrspace(1) %a
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @_Z3sinf(float) #1
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declare void @forbid_sroa(ptr addrspace(5) nocapture %p)
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attributes #0 = { noinline }
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attributes #1 = { nounwind readnone }
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