9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
56 lines
1.9 KiB
YAML
56 lines
1.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s
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# FIXME: This is a miscompile, and the s_or_b64s need to be preserved.
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---
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name: invalid_end_cf_fold_0
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tracksRegLiveness: true
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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; GXN-LABEL: name: invalid_end_cf_fold_0
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; GXN: bb.0:
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; GXN-NEXT: successors: %bb.1(0x80000000)
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; GXN-NEXT: liveins: $vgpr0, $sgpr0_sgpr1
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; GXN-NEXT: {{ $}}
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; GXN-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
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; GXN-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $exec
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; GXN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
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; GXN-NEXT: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $exec
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; GXN-NEXT: {{ $}}
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; GXN-NEXT: bb.1:
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; GXN-NEXT: successors: %bb.2(0x80000000)
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; GXN-NEXT: {{ $}}
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; GXN-NEXT: $exec = S_OR_B64 $exec, [[COPY1]], implicit-def $scc
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; GXN-NEXT: {{ $}}
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; GXN-NEXT: bb.2:
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; GXN-NEXT: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
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; GXN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GXN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GXN-NEXT: DS_WRITE_B32 [[DEF]], [[DEF1]], 0, 0, implicit $m0, implicit $exec :: (store (s32), addrspace 3)
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; GXN-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = COPY $exec
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$exec = S_OR_B64 $exec, %0, implicit-def $scc
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%2:sgpr_64 = COPY $exec
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bb.1:
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$exec = S_OR_B64 $exec, %1, implicit-def $scc
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bb.2:
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$exec = S_OR_B64 $exec, %2, implicit-def $scc
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%5:vgpr_32 = IMPLICIT_DEF
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%6:vgpr_32 = IMPLICIT_DEF
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DS_WRITE_B32 %5, %6, 0, 0, implicit $m0, implicit $exec :: (store (s32), addrspace 3)
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S_ENDPGM 0
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...
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