9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
43 lines
1.8 KiB
LLVM
43 lines
1.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
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@lds = addrspace(3) global [512 x float] undef, align 4
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; offset0 is larger than offset1
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; SI-LABEL: {{^}}offset_order:
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI-DAG: ds_read_b64 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:8
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; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
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; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:6 offset1:248
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define amdgpu_kernel void @offset_order(ptr addrspace(1) %out) {
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entry:
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%val0 = load float, ptr addrspace(3) @lds
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%ptr1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 256
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%val1 = load float, ptr addrspace(3) %ptr1
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%add1 = fadd float %val0, %val1
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%ptr2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 3
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%val2 = load float, ptr addrspace(3) %ptr2
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%add2 = fadd float %add1, %val2
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%ptr3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 2
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%val3 = load float, ptr addrspace(3) %ptr3
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%add3 = fadd float %add2, %val3
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%ptr4 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 12
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%val4 = load float, ptr addrspace(3) %ptr4
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%add4 = fadd float %add3, %val4
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%ptr5 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 14
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%val5 = load float, ptr addrspace(3) %ptr5
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%add5 = fadd float %add4, %val5
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%ptr6 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
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%val6 = load float, ptr addrspace(3) %ptr6
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%add6 = fadd float %add5, %val6
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store float %add6, ptr addrspace(1) %out
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ret void
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}
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