9843843c88
This fixes DAG divergence mishandling inline asm. This was considering the glue nodes for divergence, when the divergence should only come from the individual CopyFromRegs that are glued. As a result, having any VGPR CopyFromRegs would taint any uniform SGPR copies as divergent, resulting in SGPR copies to VGPR virtual registers later.
366 lines
10 KiB
LLVM
366 lines
10 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK %s
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; CHECK-LABEL: {{^}}inline_asm:
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; CHECK: s_endpgm
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; CHECK: s_endpgm
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define amdgpu_kernel void @inline_asm(ptr addrspace(1) %out) {
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entry:
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store i32 5, ptr addrspace(1) %out
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call void asm sideeffect "s_endpgm", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}inline_asm_shader:
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; CHECK: s_endpgm
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; CHECK: s_endpgm
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define amdgpu_ps void @inline_asm_shader() {
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entry:
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call void asm sideeffect "s_endpgm", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}branch_on_asm_vgpr:
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; Make sure VGPR inline assembly is treated as divergent.
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; CHECK: v_mov_b32 v{{[0-9]+}}, 0
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; CHECK: v_cmp_eq_u32
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; CHECK: s_and_saveexec_b64
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define amdgpu_kernel void @branch_on_asm_vgpr(ptr addrspace(1) %out) {
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%zero = call i32 asm "v_mov_b32 $0, 0", "=v"()
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%cmp = icmp eq i32 %zero, 0
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br i1 %cmp, label %if, label %endif
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if:
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store i32 0, ptr addrspace(1) %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}branch_on_asm_sgpr:
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; Make sure SGPR inline assembly is treated as uniform
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; CHECK: s_mov_b32 s{{[0-9]+}}, 0
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; CHECK: s_cmp_lg_u32
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; CHECK: s_cbranch_scc0
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define amdgpu_kernel void @branch_on_asm_sgpr(ptr addrspace(1) %out) {
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%zero = call i32 asm "s_mov_b32 $0, 0", "=s"()
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%cmp = icmp eq i32 %zero, 0
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br i1 %cmp, label %if, label %endif
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if:
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store i32 0, ptr addrspace(1) %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}v_cmp_asm:
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; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
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; CHECK: v_cmp_ne_u32_e64 s[[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]], 0, [[SRC]]
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; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
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; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]
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; CHECK: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]
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define amdgpu_kernel void @v_cmp_asm(ptr addrspace(1) %out, i32 %in) {
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%sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in)
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store i64 %sgpr, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm:
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; CHECK: codeLenInByte = 12
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define amdgpu_kernel void @code_size_inline_asm(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "v_nop_e64", ""()
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ret void
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}
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; All inlineasm instructions are assumed to be the maximum size
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; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:
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; CHECK: codeLenInByte = 12
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define amdgpu_kernel void @code_size_inline_asm_small_inst(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "v_nop_e32", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_2_inst(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "
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v_nop_e64
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v_nop_e64
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "
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v_nop_e64
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v_nop_e64
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_0_inst(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_1_comment(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "
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; comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_2_comments_line(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; first comment ; second comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; first comment;second comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; comment
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v_nop_e64 ; inline comment
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; separate comment
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v_nop_e64
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "v_nop_e64 ; inline comment
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; separate comment
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v_nop_e64
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(ptr addrspace(1) %out) {
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entry:
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call void asm sideeffect "; comment
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v_add_i32_e32 v0, vcc, v1, v2 ; inline comment
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; separate comment
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v_bfrev_b32_e32 v0, 1
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; FIXME: Should not have intermediate sgprs
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; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr:
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; CHECK: v_mov_b32_e32 v0, 0x1e240
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; CHECK: v_mov_b32_e32 v1, 0
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; CHECK: use v[0:1]
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define amdgpu_kernel void @i64_imm_input_phys_vgpr() {
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entry:
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call void asm sideeffect "; use $0 ", "{v[0:1]}"(i64 123456)
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ret void
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}
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; CHECK-LABEL: {{^}}i1_imm_input_phys_vgpr:
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; CHECK: v_mov_b32_e32 v0, 1{{$}}
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; CHECK: ; use v0
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define amdgpu_kernel void @i1_imm_input_phys_vgpr() {
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entry:
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call void asm sideeffect "; use $0 ", "{v0}"(i1 true)
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ret void
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}
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; FIXME: This behavior is nonsense. We should probably disallow i1 asm
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; CHECK-LABEL: {{^}}i1_input_phys_vgpr:
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; CHECK: {{buffer|flat}}_load_ubyte [[LOAD:v[0-9]+]]
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; CHECK-NOT: [[LOAD]]
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; CHECK: ; use v0
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; CHECK: v_and_b32_e32 [[STORE:v[0-9]+]], 1, v1
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; CHECK: {{buffer|flat}}_store_byte [[STORE]],
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define amdgpu_kernel void @i1_input_phys_vgpr() {
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entry:
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%val = load i1, ptr addrspace(1) undef
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%cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val)
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store i1 %cc, ptr addrspace(1) undef
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ret void
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}
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; FIXME: Should prodbably be masking high bits of load.
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; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2:
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; CHECK: buffer_load_ubyte v0
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; CHECK-NEXT: s_waitcnt
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; CHECK-NEXT: buffer_load_ubyte v1
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; CHECK-NEXT: s_waitcnt
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; CHECK-NEXT: ASMSTART
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define amdgpu_kernel void @i1_input_phys_vgpr_x2() {
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entry:
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%val0 = load volatile i1, ptr addrspace(1) undef
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%val1 = load volatile i1, ptr addrspace(1) undef
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call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)
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ret void
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}
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; CHECK-LABEL: {{^}}muliple_def_phys_vgpr:
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; CHECK: ; def v0
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; CHECK: v_mov_b32_e32 v1, v0
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; CHECK: ; def v0
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; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1
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define amdgpu_kernel void @muliple_def_phys_vgpr() {
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entry:
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%def0 = call i32 asm sideeffect "; def $0 ", "={v0}"()
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%def1 = call i32 asm sideeffect "; def $0 ", "={v0}"()
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%add = shl i32 %def0, %def1
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store i32 %add, ptr addrspace(1) undef
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ret void
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}
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; CHECK-LABEL: {{^}}asm_constraint_c_n:
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; CHECK: s_trap 10{{$}}
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define amdgpu_kernel void @asm_constraint_c_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
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ret void
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}
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; CHECK-LABEL: {{^}}asm_constraint_n_n:
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; CHECK: s_trap -10{{$}}
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define amdgpu_kernel void @asm_constraint_n_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
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ret void
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}
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; Make sure tuples of 3 SGPRs are printed with the [] syntax instead
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; of the tablegen default.
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; CHECK-LABEL: {{^}}sgpr96_name_format:
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; CHECK: ; sgpr96 s[0:2]
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define amdgpu_kernel void @sgpr96_name_format() {
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entry:
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tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
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ret void
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}
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; Check aggregate types are handled properly.
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; CHECK-LABEL: mad_u64
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; CHECK: v_mad_u64_u32
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define void @mad_u64(i32 %x, i1 %c0) {
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entry:
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br i1 %c0, label %exit, label %false
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false:
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%s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0)
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br label %exit
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exit:
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%s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false]
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%v0 = extractvalue { i64, i64 } %s1, 0
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%v1 = extractvalue { i64, i64 } %s1, 1
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tail call void asm sideeffect "; use $0", "v"(i64 %v0)
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tail call void asm sideeffect "; use $0", "v"(i64 %v1)
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ret void
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}
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; CHECK-LABEL: {{^}}scc_as_i32:
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; CHECK: ; def scc
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; CHECK: ; use scc
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define void @scc_as_i32() {
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%scc = call i32 asm sideeffect "; def $0", "={scc}"()
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call void asm sideeffect "; use $0 ", "{scc}"(i32 %scc)
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ret void
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}
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; CHECK-LABEL: {{^}}scc_as_i1:
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; CHECK: ; def scc
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; CHECK: ; use scc
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define void @scc_as_i1() {
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%scc = call i1 asm sideeffect "; def $0", "={scc}"()
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call void asm sideeffect "; use $0 ", "{scc}"(i1 %scc)
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ret void
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}
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; Make sure the SGPR def is treated as a uniform value when the inline
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; assembly also defines a divergent value. The add should be scalar
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; and not introduce illegal vgpr to sgpr copies.
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; CHECK-LABEL: {{^}}mixed_def_vgpr_sgpr_def_asm:
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; CHECK: ; def v0 s[4:5]
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; CHECK: s_add_u32
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; CHECK-NEXT: s_addc_u32
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; CHECK: ; use s[4:5]
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define void @mixed_def_vgpr_sgpr_def_asm() {
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%vgpr_sgpr = call { i32, i64 } asm sideeffect "; def $0 $1 ", "=v,={s[4:5]}"()
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%vgpr = extractvalue { i32, i64 } %vgpr_sgpr, 0
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%sgpr = extractvalue { i32, i64 } %vgpr_sgpr, 1
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%sgpr.add = add i64 %sgpr, 2
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call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)
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ret void
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}
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; CHECK-LABEL: {{^}}mixed_def_sgpr_vgpr_def_asm:
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; CHECK: ; def s[4:5] v0
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; CHECK: s_add_u32
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; CHECK-NEXT: s_addc_u32
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; CHECK: ; use s[4:5]
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define void @mixed_def_sgpr_vgpr_def_asm() {
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%sgpr_vgpr = call { i64, i32 } asm sideeffect "; def $0 $1 ", "={s[4:5]},=v"()
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%sgpr = extractvalue { i64, i32 } %sgpr_vgpr, 0
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%vgpr = extractvalue { i64, i32 } %sgpr_vgpr, 1
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%sgpr.add = add i64 %sgpr, 2
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call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)
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ret void
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}
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