1ceccbb0dd
If an undef subregister def is live into another block, we need to
maintain a physreg def to track the liveness of those lanes. This
would manifest a verifier error after branch folding, when the cloned
tail block use no longer had a def.
We need to detect interference with other assigned intervals to avoid
clobbering the undef lanes defined in other intervals, since the undef
def didn't count as interference. This is pretty ugly and adds a new
dependency on LiveRegMatrix, keeping it live for one more pass. It also
adds a lot of implicit operand spam (we really should have a better
representation for this).
There is a missing verifier check for this situation. Added an xfailed
test that demonstrates this. We may also be able to revert the changes
in 47d3cbcf84.
It might be better to insert an IMPLICIT_DEF before the instruction
rather than using the implicit-def operand.
Fixes #98474
56 lines
2.5 KiB
YAML
56 lines
2.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -start-before=greedy,2 -stop-after=tailduplication -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: undef_subreg_def_live_out_tailduplicate_vreg96_undef_sub1_sub2_assigned_physreg_interference
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; CHECK-LABEL: name: undef_subreg_def_live_out_tailduplicate_vreg96_undef_sub1_sub2_assigned_physreg_interference
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc
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; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: liveins: $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $vgpr3 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr4_vgpr5
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; CHECK-NEXT: EXP 0, killed renamable $vgpr3, renamable $vgpr4, renamable $vgpr5, killed renamable $vgpr2, 0, 0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: liveins: $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7
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; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: renamable $vgpr3_vgpr4_vgpr5 = BUFFER_LOAD_FORMAT_XYZ_IDXEN killed renamable $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
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; CHECK-NEXT: EXP 0, killed renamable $vgpr3, renamable $vgpr4, renamable $vgpr5, killed renamable $vgpr2, 0, 0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $sgpr0, $vgpr2
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%2:vgpr_32 = COPY $vgpr2
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S_CMP_EQ_U32 killed $sgpr0, 0, implicit-def $scc
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S_CBRANCH_SCC0 %bb.2, implicit killed $scc
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bb.1:
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undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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S_NOP 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%0:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_IDXEN killed %1, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), addrspace 8)
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bb.3:
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EXP 0, killed %0.sub0, killed %0.sub1, killed %0.sub2, %2:vgpr_32, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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