9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
156 lines
7.6 KiB
LLVM
156 lines
7.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX12 %s
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; GCN-LABEL: {{^}}load.f32.1d:
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; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16
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; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16
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; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
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define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v2f32.1d:
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; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16
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; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
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; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16
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define amdgpu_ps <4 x float> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v3f32.1d:
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; GFX9: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm a16
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; GFX10: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16
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; GFX12: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16
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define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v4f32.1d:
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; GFX9: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
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; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16
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; GFX12: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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define amdgpu_ps <4 x float> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.f32.2d:
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; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16
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; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16
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; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
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define amdgpu_ps <4 x float> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v2f32.2d:
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; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16
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; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16
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; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16
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define amdgpu_ps <4 x float> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v3f32.2d:
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; GFX9: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm a16
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; GFX10: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16
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; GFX12: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16
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define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v4f32.2d:
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; GFX9: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
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; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16
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; GFX12: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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define amdgpu_ps <4 x float> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.f32.3d:
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; GFX9: image_load v0, v[0:1], s[0:7] dmask:0x1 unorm a16
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; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16
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; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
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define amdgpu_ps <4 x float> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v2f32.3d:
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; GFX9: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16
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; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16
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; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
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define amdgpu_ps <4 x float> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v3f32.3d:
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; GFX9: image_load v[0:2], v[0:1], s[0:7] dmask:0x7 unorm a16
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; GFX10: image_load v[0:2], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16
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; GFX12: image_load v[0:2], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16
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define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load.v4f32.3d:
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; GFX9: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
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; GFX10: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
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; GFX12: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
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define amdgpu_ps <4 x float> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
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declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #2
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declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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