9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test that we correctly commute a sub instruction
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; FUNC-LABEL: {{^}}sub_rev:
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; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, vcc, s
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; SI: v_subrev_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, s
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; ModuleID = 'vop-shrink.ll'
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define amdgpu_kernel void @sub_rev(ptr addrspace(1) %out, <4 x i32> %sgpr, i32 %cond) {
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entry:
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%vgpr = call i32 @llvm.amdgcn.workitem.id.x() #1
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%tmp = icmp eq i32 %cond, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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%tmp2 = extractelement <4 x i32> %sgpr, i32 1
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store i32 %tmp2, ptr addrspace(1) %out
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br label %endif
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else: ; preds = %entry
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%tmp3 = extractelement <4 x i32> %sgpr, i32 2
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%tmp4 = sub i32 %vgpr, %tmp3
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store i32 %tmp4, ptr addrspace(1) %out
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br label %endif
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endif: ; preds = %else, %if
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ret void
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}
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; Test that we fold an immediate that was illegal for a 64-bit op into the
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; 32-bit op when we shrink it.
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; FUNC-LABEL: {{^}}add_fold:
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; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000
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define amdgpu_kernel void @add_fold(ptr addrspace(1) %out) {
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entry:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = uitofp i32 %tmp to float
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%tmp2 = fadd float %tmp1, 1.024000e+03
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store float %tmp2, ptr addrspace(1) %out
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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