5f5f566b26
It seems to be a hardware defect that the half inline constants do not work as expected for the 16-bit integer operations (the inverse does work correctly). Experimentation seems to show these are really reading the 32-bit inline constants, which can be observed by writing inline asm using op_sel to see what's in the high half of the constant. Theoretically we could fold the high halves of the 32-bit constants using op_sel. The *_asm_all.s MC tests are broken, and I don't know where the script to autogenerate these are. I started manually fixing it, but there's just too many cases to fix. This also does break the assembler/disassembler support for these values, and I'm not sure what to do about it. These are still valid encodings, so it seems like you should be able to use them in some way. If you wrote assembly using them, you could have really meant it (perhaps to read the high bits with op_sel?). The disassembler will print the invalid literal constant which will fail to re-assemble. The behavior is also different depending on the use context. Consider this example, which was previously accepted and encoded using the inline constant: v_mad_i16 v5, v1, -4.0, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04] In contexts where an inline immediate is required (such as on gfx8/9), this will now be rejected. For gfx10, this will produce the literal encoding and change the printed format: v_mad_i16 v5, v1, 0xc400, v3 ; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00] This is just another variation of the issue that we don't perfectly handle round trip assembly/disassembly due to not tracking how immediates were encoded. This doesn't matter much in practice, since compilers don't emit the suboptimal encoding. I doubt any users are relying on this behavior (although I did make use of the old behavior to figure out what was wrong). Fixes bug 46302.
533 lines
17 KiB
C++
533 lines
17 KiB
C++
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// The SI code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <cstdlib>
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using namespace llvm;
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namespace {
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class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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const MCRegisterInfo &MRI;
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/// Encode an fp or int literal
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uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
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const MCSubtargetInfo &STI) const;
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public:
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SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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MCContext &ctx)
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: AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
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SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
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SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
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/// Encode the instruction and write it to the OS.
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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/// \returns the encoding for an MCOperand.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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/// Use a fixup to encode the simm16 field for SOPP branch
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/// instructions.
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unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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unsigned getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new SIMCCodeEmitter(MCII, MRI, Ctx);
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}
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// Returns the encoding value to use if the given integer is an integer inline
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// immediate value, or 0 if it is not.
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template <typename IntTy>
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static uint32_t getIntInlineImmEncoding(IntTy Imm) {
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if (Imm >= 0 && Imm <= 64)
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return 128 + Imm;
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if (Imm >= -16 && Imm <= -1)
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return 192 + std::abs(Imm);
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return 0;
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}
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static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) {
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uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
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return IntImm == 0 ? 255 : IntImm;
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}
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static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
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uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == 0x3800) // 0.5
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return 240;
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if (Val == 0xB800) // -0.5
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return 241;
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if (Val == 0x3C00) // 1.0
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return 242;
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if (Val == 0xBC00) // -1.0
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return 243;
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if (Val == 0x4000) // 2.0
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return 244;
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if (Val == 0xC000) // -2.0
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return 245;
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if (Val == 0x4400) // 4.0
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return 246;
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if (Val == 0xC400) // -4.0
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return 247;
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if (Val == 0x3118 && // 1.0 / (2.0 * pi)
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STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
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return 248;
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return 255;
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}
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static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == FloatToBits(0.5f))
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return 240;
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if (Val == FloatToBits(-0.5f))
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return 241;
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if (Val == FloatToBits(1.0f))
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return 242;
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if (Val == FloatToBits(-1.0f))
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return 243;
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if (Val == FloatToBits(2.0f))
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return 244;
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if (Val == FloatToBits(-2.0f))
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return 245;
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if (Val == FloatToBits(4.0f))
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return 246;
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if (Val == FloatToBits(-4.0f))
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return 247;
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if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
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STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
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return 248;
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return 255;
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}
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static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == DoubleToBits(0.5))
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return 240;
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if (Val == DoubleToBits(-0.5))
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return 241;
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if (Val == DoubleToBits(1.0))
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return 242;
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if (Val == DoubleToBits(-1.0))
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return 243;
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if (Val == DoubleToBits(2.0))
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return 244;
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if (Val == DoubleToBits(-2.0))
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return 245;
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if (Val == DoubleToBits(4.0))
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return 246;
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if (Val == DoubleToBits(-4.0))
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return 247;
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if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
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STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
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return 248;
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return 255;
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}
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uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
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const MCOperandInfo &OpInfo,
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const MCSubtargetInfo &STI) const {
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int64_t Imm;
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if (MO.isExpr()) {
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const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
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if (!C)
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return 255;
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Imm = C->getValue();
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} else {
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assert(!MO.isFPImm());
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if (!MO.isImm())
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return ~0;
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Imm = MO.getImm();
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}
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switch (OpInfo.OperandType) {
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case AMDGPU::OPERAND_REG_IMM_INT32:
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case AMDGPU::OPERAND_REG_IMM_FP32:
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case AMDGPU::OPERAND_REG_INLINE_C_INT32:
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case AMDGPU::OPERAND_REG_INLINE_C_FP32:
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case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
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case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
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return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_INT64:
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case AMDGPU::OPERAND_REG_IMM_FP64:
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case AMDGPU::OPERAND_REG_INLINE_C_INT64:
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case AMDGPU::OPERAND_REG_INLINE_C_FP64:
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return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_INT16:
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case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
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return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_FP16:
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case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
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// FIXME Is this correct? What do inline immediates do on SI for f16 src
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// which does not have f16 support?
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return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_V2INT16:
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case AMDGPU::OPERAND_REG_IMM_V2FP16: {
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if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])
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return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
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if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)
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return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
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LLVM_FALLTHROUGH;
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}
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case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
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case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
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return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
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case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
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uint16_t Lo16 = static_cast<uint16_t>(Imm);
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uint32_t Encoding = getLit16Encoding(Lo16, STI);
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return Encoding;
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}
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default:
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llvm_unreachable("invalid operand size");
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}
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}
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void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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unsigned bytes = Desc.getSize();
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for (unsigned i = 0; i < bytes; i++) {
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OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
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}
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// NSA encoding.
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if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
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int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::vaddr0);
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int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::srsrc);
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assert(vaddr0 >= 0 && srsrc > vaddr0);
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unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
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unsigned NumPadding = (-NumExtraAddrs) & 3;
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for (unsigned i = 0; i < NumExtraAddrs; ++i)
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OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
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Fixups, STI));
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for (unsigned i = 0; i < NumPadding; ++i)
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OS.write(0);
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}
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if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||
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(bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))
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return;
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// Check for additional literals in SRC0/1/2 (Op 1/2/3)
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for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
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// Check if this operand should be encoded as [SV]Src
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if (!AMDGPU::isSISrcOperand(Desc, i))
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continue;
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// Is this operand a literal immediate?
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const MCOperand &Op = MI.getOperand(i);
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if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
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continue;
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// Yes! Encode it
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int64_t Imm = 0;
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if (Op.isImm())
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Imm = Op.getImm();
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else if (Op.isExpr()) {
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if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
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Imm = C->getValue();
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} else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
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llvm_unreachable("Must be immediate or expr");
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for (unsigned j = 0; j < 4; j++) {
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OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
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}
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// Only one literal value allowed
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break;
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}
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}
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unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
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Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
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return 0;
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}
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return getMachineOpValue(MI, MO, Fixups, STI);
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}
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unsigned SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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auto Offset = MI.getOperand(OpNo).getImm();
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// VI only supports 20-bit unsigned offsets.
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assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
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return Offset;
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}
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unsigned
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SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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using namespace AMDGPU::SDWA;
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uint64_t RegEnc = 0;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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RegEnc |= MRI.getEncodingValue(Reg);
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RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
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if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
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RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
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}
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return RegEnc;
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} else {
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
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if (Enc != ~0U && Enc != 255) {
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return Enc | SDWA9EncValues::SRC_SGPR_MASK;
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}
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}
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llvm_unreachable("Unsupported operand kind");
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return 0;
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}
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unsigned
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SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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using namespace AMDGPU::SDWA;
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uint64_t RegEnc = 0;
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const MCOperand &MO = MI.getOperand(OpNo);
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unsigned Reg = MO.getReg();
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if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
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RegEnc |= MRI.getEncodingValue(Reg);
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RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
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RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
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}
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return RegEnc;
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}
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unsigned
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SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned Reg = MI.getOperand(OpNo).getReg();
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uint64_t Enc = MRI.getEncodingValue(Reg);
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// VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
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// instructions use acc[0:1] modifier bits to distinguish. These bits are
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// encoded as a virtual 9th bit of the register for these operands.
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if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
|
|
Enc |= 512;
|
|
|
|
return Enc;
|
|
}
|
|
|
|
static bool needsPCRel(const MCExpr *Expr) {
|
|
switch (Expr->getKind()) {
|
|
case MCExpr::SymbolRef: {
|
|
auto *SE = cast<MCSymbolRefExpr>(Expr);
|
|
MCSymbolRefExpr::VariantKind Kind = SE->getKind();
|
|
return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO &&
|
|
Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
|
|
}
|
|
case MCExpr::Binary: {
|
|
auto *BE = cast<MCBinaryExpr>(Expr);
|
|
if (BE->getOpcode() == MCBinaryExpr::Sub)
|
|
return false;
|
|
return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
|
|
}
|
|
case MCExpr::Unary:
|
|
return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
|
|
case MCExpr::Target:
|
|
case MCExpr::Constant:
|
|
return false;
|
|
}
|
|
llvm_unreachable("invalid kind");
|
|
}
|
|
|
|
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
|
|
const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
if (MO.isReg())
|
|
return MRI.getEncodingValue(MO.getReg());
|
|
|
|
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
|
|
// FIXME: If this is expression is PCRel or not should not depend on what
|
|
// the expression looks like. Given that this is just a general expression,
|
|
// it should probably be FK_Data_4 and whatever is producing
|
|
//
|
|
// s_add_u32 s2, s2, (extern_const_addrspace+16
|
|
//
|
|
// And expecting a PCRel should instead produce
|
|
//
|
|
// .Ltmp1:
|
|
// s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
|
|
MCFixupKind Kind;
|
|
if (needsPCRel(MO.getExpr()))
|
|
Kind = FK_PCRel_4;
|
|
else
|
|
Kind = FK_Data_4;
|
|
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
uint32_t Offset = Desc.getSize();
|
|
assert(Offset == 4 || Offset == 8);
|
|
|
|
Fixups.push_back(
|
|
MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
|
|
}
|
|
|
|
// Figure out the operand number, needed for isSrcOperand check
|
|
unsigned OpNo = 0;
|
|
for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
|
|
if (&MO == &MI.getOperand(OpNo))
|
|
break;
|
|
}
|
|
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
|
|
uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
|
|
if (Enc != ~0U &&
|
|
(Enc != 255 || Desc.getSize() == 4 || Desc.getSize() == 8))
|
|
return Enc;
|
|
|
|
} else if (MO.isImm())
|
|
return MO.getImm();
|
|
|
|
llvm_unreachable("Encoding of this operand type is not supported yet.");
|
|
return 0;
|
|
}
|
|
|
|
#define ENABLE_INSTR_PREDICATE_VERIFIER
|
|
#include "AMDGPUGenMCCodeEmitter.inc"
|