sstwcw fbef1f835f [clang-format][NFC] Make formatting Verilog faster (#121139) ...

A regular expression was used in the lexing process. It made the program
take more than linear time with regards to the length of the input. It
looked like the entire buffer could be scanned for every token lexed.
Now the regular expression is replaced with code. Previously it took 20
minutes for the program to format 125 000 lines of code on my computer.
Now it takes 315 milliseconds.

2025-01-14 15:37:06 +00:00

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