Sid Manning 0d7e5daedc [lld][Hexagon] Add checks for instructions that can have TLS relocations ...

Several instructions with potential TLS relocations were missing.  This
issue was found when building the Canadian LLVM toolchain.

2021-09-01 13:15:18 -07:00

..

AArch64.cpp

[ELF][AArch64] Write addends for TLSDESC relocations with -z rel

2021-07-09 10:41:41 +01:00

AMDGPU.cpp

[lld][AMDGPU] Handle R_AMDGPU_REL16 relocation.

2021-07-13 20:41:11 +01:00

ARM.cpp

[ELF] Check the Elf_Rel addends for dynamic relocations

2021-07-09 10:41:40 +01:00

AVR.cpp

[ELF][AVR] Add explicit relocation types to getRelExpr

2021-05-12 12:38:27 -07:00

Hexagon.cpp

[lld][Hexagon] Add checks for instructions that can have TLS relocations

2021-09-01 13:15:18 -07:00

Mips.cpp

[ELF] Check the Elf_Rel addends for dynamic relocations

2021-07-09 10:41:40 +01:00

MipsArchTree.cpp

…

MSP430.cpp

…

PPC64.cpp

[LLD][PowerPC] Fix bug in PC-Relative initial exec

2021-03-22 13:15:44 -05:00

PPC.cpp

[ELF] Support R_PPC_ADDR24 (ba foo; bla foo)

2021-01-17 00:02:13 -08:00

PPCInsns.def

…

RISCV.cpp

[ELF] Implement RISCV::getImplicitAddend()

2021-07-09 10:41:40 +01:00

SPARCV9.cpp

[ELF] Rename R_TLS to R_TPREL and R_NEG_TLS to R_TPREL_NEG. NFC

2020-12-18 08:24:42 -08:00

X86_64.cpp

[ELF] Write R_X86_64_IRELATIVE addends with -z rel

2021-07-09 10:41:40 +01:00

X86.cpp

[ELF] Check the Elf_Rel addends for dynamic relocations

2021-07-09 10:41:40 +01:00