657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
198 lines
5.1 KiB
LLVM
198 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=m68k-linux-gnu -verify-machineinstrs \
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; RUN: -code-model=medium -relocation-model=pic \
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; RUN: | FileCheck %s
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@ptr = external global i32*
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@dst = external global i32
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@src = external global i32
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define void @test0() nounwind {
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; CHECK-LABEL: test0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (dst@GOTPCREL,%pc), %a0
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; CHECK-NEXT: move.l (ptr@GOTPCREL,%pc), %a1
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; CHECK-NEXT: move.l %a0, (%a1)
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; CHECK-NEXT: move.l (src@GOTPCREL,%pc), %a1
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; CHECK-NEXT: move.l (%a1), (%a0)
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; CHECK-NEXT: rts
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entry:
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store i32* @dst, i32** @ptr
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%tmp.s = load i32, i32* @src
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store i32 %tmp.s, i32* @dst
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ret void
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}
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@ptr2 = global i32* null
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@dst2 = global i32 0
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@src2 = global i32 0
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define void @test1() nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (dst2@GOTPCREL,%pc), %a0
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; CHECK-NEXT: move.l (ptr2@GOTPCREL,%pc), %a1
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; CHECK-NEXT: move.l %a0, (%a1)
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; CHECK-NEXT: move.l (src2@GOTPCREL,%pc), %a1
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; CHECK-NEXT: move.l (%a1), (%a0)
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; CHECK-NEXT: rts
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entry:
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store i32* @dst2, i32** @ptr2
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%tmp.s = load i32, i32* @src2
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store i32 %tmp.s, i32* @dst2
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ret void
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}
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declare i8* @malloc(i32)
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define void @test2() nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: move.l #40, (%sp)
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; CHECK-NEXT: jsr (malloc@PLT,%pc)
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%ptr = call i8* @malloc(i32 40)
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ret void
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}
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@pfoo = external global void(...)*
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declare void(...)* @afoo(...)
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define void @test3() nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: jsr (afoo@PLT,%pc)
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; CHECK-NEXT: move.l %d0, %a0
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; CHECK-NEXT: move.l (pfoo@GOTPCREL,%pc), %a1
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; CHECK-NEXT: move.l %a0, (%a1)
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; CHECK-NEXT: jsr (%a0)
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%tmp = call void(...)*(...) @afoo()
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store void(...)* %tmp, void(...)** @pfoo
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%tmp1 = load void(...)*, void(...)** @pfoo
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call void(...) %tmp1()
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ret void
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}
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declare void @foo(...)
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define void @test4() nounwind {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: jsr (foo@PLT,%pc)
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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call void(...) @foo()
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ret void
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}
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@ptr6 = internal global i32* null
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@dst6 = internal global i32 0
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@src6 = internal global i32 0
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define void @test5() nounwind {
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; CHECK-LABEL: test5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
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; CHECK-NEXT: move.l %a0, %a1
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; CHECK-NEXT: adda.l #dst6@GOTOFF, %a1
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; CHECK-NEXT: move.l #ptr6@GOTOFF, %d0
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; CHECK-NEXT: move.l %a1, (0,%a0,%d0)
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; CHECK-NEXT: move.l #src6@GOTOFF, %d0
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; CHECK-NEXT: move.l #dst6@GOTOFF, %d1
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; CHECK-NEXT: move.l (0,%a0,%d0), (0,%a0,%d1)
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; CHECK-NEXT: rts
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entry:
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store i32* @dst6, i32** @ptr6
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%tmp.s = load i32, i32* @src6
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store i32 %tmp.s, i32* @dst6
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ret void
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}
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define void @test7(i32 %n.u) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: add.l #-1, %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: sub.l #12, %d1
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; CHECK-NEXT: bhi .LBB6_12
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
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; CHECK-NEXT: lsl.l #2, %d0
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; CHECK-NEXT: move.l %a0, %a1
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; CHECK-NEXT: adda.l #.LJTI6_0@GOTOFF, %a1
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; CHECK-NEXT: move.l %a0, %d1
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; CHECK-NEXT: add.l (0,%a1,%d0), %d1
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; CHECK-NEXT: move.l %d1, %a0
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; CHECK-NEXT: jmp (%a0)
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; CHECK-NEXT: .LBB6_12: ; %bb2
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; CHECK-NEXT: bra foo6@PLT ; TAILCALL
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; CHECK-NEXT: .LBB6_3: ; %bb6
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; CHECK-NEXT: bra foo1@PLT ; TAILCALL
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; CHECK-NEXT: .LBB6_8: ; %bb1
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; CHECK-NEXT: bra foo2@PLT ; TAILCALL
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; CHECK-NEXT: .LBB6_9: ; %bb3
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; CHECK-NEXT: bra foo3@PLT ; TAILCALL
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; CHECK-NEXT: .LBB6_10: ; %bb4
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; CHECK-NEXT: bra foo4@PLT ; TAILCALL
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; CHECK-NEXT: .LBB6_14: ; %bb11
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; CHECK-NEXT: bra foo5@PLT ; TAILCALL
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entry:
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switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
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bb:
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tail call void(...) @foo1()
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ret void
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bb1:
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tail call void(...) @foo2()
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ret void
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bb2:
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tail call void(...) @foo6()
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ret void
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bb3:
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tail call void(...) @foo3()
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ret void
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bb4:
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tail call void(...) @foo4()
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ret void
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bb5:
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tail call void(...) @foo5()
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ret void
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bb6:
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tail call void(...) @foo1()
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ret void
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bb7:
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tail call void(...) @foo2()
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ret void
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bb8:
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tail call void(...) @foo6()
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ret void
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bb9:
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tail call void(...) @foo3()
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ret void
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bb10:
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tail call void(...) @foo4()
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ret void
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bb11:
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tail call void(...) @foo5()
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ret void
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bb12:
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tail call void(...) @foo6()
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ret void
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}
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declare void @foo1(...)
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declare void @foo2(...)
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declare void @foo6(...)
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declare void @foo3(...)
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declare void @foo4(...)
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declare void @foo5(...)
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