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clang-p2996/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
David Green 9cb8f4d1ad [ARM] Add a tail-predication loop predicate register 
The semantics of tail predication loops means that the value of LR as an
instruction is executed determines the predicate. In other words:

mov r3, #3
DLSTP lr, r3        // Start tail predication, lr==3
VADD.s32 q0, q1, q2 // Lanes 0,1 and 2 are updated in q0.
mov lr, #1
VADD.s32 q0, q1, q2 // Only first lane is updated.

This means that the value of lr cannot be spilled and re-used in tail
predication regions without potentially altering the behaviour of the
program. More lanes than required could be stored, for example, and in
the case of a gather those lanes might not have been setup, leading to
alignment exceptions.

This patch adds a new lr predicate operand to MVE instructions in order
to keep a reference to the lr that they use as a tail predicate. It will
usually hold the zeroreg meaning not predicated, being set to the LR phi
value in the MVETPAndVPTOptimisationsPass. This will prevent it from
being spilled anywhere that it needs to be used.

A lot of tests needed updating.

Differential Revision: https://reviews.llvm.org/D107638
2021-09-02 13:42:58 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
--- |
define dso_local arm_aapcs_vfpcc void @skip_debug(i32* nocapture %a, i16* nocapture readonly %b, i32 %N) !dbg !8 {
entry:
call void @llvm.dbg.value(metadata i32* %a, metadata !17, metadata !DIExpression()), !dbg !23
call void @llvm.dbg.value(metadata i16* %b, metadata !18, metadata !DIExpression()), !dbg !23
call void @llvm.dbg.value(metadata i32 %N, metadata !19, metadata !DIExpression()), !dbg !23
%0 = load i32, i32* %a, align 4, !dbg !24
call void @llvm.dbg.value(metadata i32 %0, metadata !20, metadata !DIExpression()), !dbg !23
call void @llvm.dbg.value(metadata i32 0, metadata !21, metadata !DIExpression()), !dbg !29
%cmp7 = icmp eq i32 %N, 0, !dbg !30
%1 = add i32 %N, 3, !dbg !32
%2 = lshr i32 %1, 2, !dbg !32
%3 = shl nuw i32 %2, 2, !dbg !32
%4 = add i32 %3, -4, !dbg !32
%5 = lshr i32 %4, 2, !dbg !32
%6 = add nuw nsw i32 %5, 1, !dbg !32
br i1 %cmp7, label %for.cond.cleanup, label %vector.ph, !dbg !32
vector.ph: ; preds = %entry
%7 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %0, i32 0, !dbg !32
%start = call i32 @llvm.start.loop.iterations.i32(i32 %6), !dbg !32
%8 = shl i32 %5, 2, !dbg !32
%9 = sub i32 %N, %8, !dbg !32
br label %vector.body, !dbg !32
vector.body: ; preds = %vector.body, %vector.ph
%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %b, %vector.ph ], !dbg !33
%vec.phi = phi <4 x i32> [ %7, %vector.ph ], [ %15, %vector.body ]
%10 = phi i32 [ %start, %vector.ph ], [ %16, %vector.body ]
%11 = phi i32 [ %N, %vector.ph ], [ %13, %vector.body ]
%lsr.iv14 = bitcast i16* %lsr.iv to <4 x i16>*
%12 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %11), !dbg !34
%13 = sub i32 %11, 4, !dbg !34
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv14, i32 2, <4 x i1> %12, <4 x i16> undef), !dbg !34
%14 = sext <4 x i16> %wide.masked.load to <4 x i32>, !dbg !34
%15 = sub <4 x i32> %vec.phi, %14, !dbg !38
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4, !dbg !33
%16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1), !dbg !33
%17 = icmp ne i32 %16, 0, !dbg !33
br i1 %17, label %vector.body, label %middle.block, !dbg !33
middle.block: ; preds = %vector.body
%vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]
%.lcssa = phi <4 x i32> [ %15, %vector.body ], !dbg !38
%18 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %9), !dbg !34
%19 = select <4 x i1> %18, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !38
%20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !32
br label %for.cond.cleanup, !dbg !42
for.cond.cleanup: ; preds = %middle.block, %entry
%temp.0.lcssa = phi i32 [ %0, %entry ], [ %20, %middle.block ], !dbg !23
call void @llvm.dbg.value(metadata i32 %temp.0.lcssa, metadata !20, metadata !DIExpression()), !dbg !23
store i32 %temp.0.lcssa, i32* %a, align 4, !dbg !42
ret void, !dbg !43
}
declare void @llvm.dbg.value(metadata, metadata, metadata)
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
declare i32 @llvm.start.loop.iterations.i32(i32)
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5, !6}
!llvm.ident = !{!7}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "skip-debug", directory: "")
!2 = !{}
!3 = !{i32 7, !"Dwarf Version", i32 4}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
!6 = !{i32 1, !"min_enum_size", i32 4}
!7 = !{!""}
!8 = distinct !DISubprogram(name: "skip_debug", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
!9 = !DISubroutineType(types: !10)
!10 = !{null, !11, !13, !15}
!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32)
!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32)
!14 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
!15 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
!16 = !{!17, !18, !19, !20, !21}
!17 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)
!18 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 2, type: !13)
!19 = !DILocalVariable(name: "N", arg: 3, scope: !8, file: !1, line: 2, type: !15)
!20 = !DILocalVariable(name: "temp", scope: !8, file: !1, line: 3, type: !12)
!21 = !DILocalVariable(name: "i", scope: !22, file: !1, line: 4, type: !15)
!22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 4, column: 3)
!23 = !DILocation(line: 0, scope: !8)
!24 = !DILocation(line: 3, column: 14, scope: !8)
!25 = !{!26, !26, i64 0}
!26 = !{!"int", !27, i64 0}
!27 = !{!"omnipotent char", !28, i64 0}
!28 = !{!"Simple C/C++ TBAA"}
!29 = !DILocation(line: 0, scope: !22)
!30 = !DILocation(line: 4, column: 26, scope: !31)
!31 = distinct !DILexicalBlock(scope: !22, file: !1, line: 4, column: 3)
!32 = !DILocation(line: 4, column: 3, scope: !22)
!33 = !DILocation(line: 4, column: 31, scope: !31)
!34 = !DILocation(line: 5, column: 13, scope: !35)
!35 = distinct !DILexicalBlock(scope: !31, file: !1, line: 4, column: 36)
!36 = !{!37, !37, i64 0}
!37 = !{!"short", !27, i64 0}
!38 = !DILocation(line: 5, column: 10, scope: !35)
!39 = distinct !{!39, !32, !40, !41}
!40 = !DILocation(line: 6, column: 3, scope: !22)
!41 = !{!"llvm.loop.isvectorized", i32 1}
!42 = !DILocation(line: 7, column: 6, scope: !8)
!43 = !DILocation(line: 8, column: 1, scope: !8)
...
---
name: skip_debug
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 16
offsetAdjustment: -8
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: skip_debug
; CHECK: bb.0.entry:
; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load (s32) from %ir.a)
; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
; CHECK: tCBZ $r2, %bb.4, debug-location !28
; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !28
; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !30
; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !30
; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $q0, $q1, $r0, $r3
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !32
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !28
; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $r0, $r12
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a)
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r6, $lr
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
frame-setup CFI_INSTRUCTION offset $r6, -12
frame-setup CFI_INSTRUCTION offset $r4, -16
$r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load (s32) from %ir.a)
DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !29
DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
tCBZ $r2, %bb.4, debug-location !32
bb.1.vector.ph:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r12
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32
renamable $lr = t2MOVi 1, 14, $noreg, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32
renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32
renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32
renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32
$lr = t2DoLoopStart renamable $lr, debug-location !32
bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !34
DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1
MVE_VPST 8, implicit $vpr, debug-location !34
renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !34 :: (load (s64) from %ir.lsr.iv14, align 2)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34
renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !34
renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33
renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !38
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33
tB %bb.3, 14, $noreg, debug-location !33
bb.3.middle.block:
successors: %bb.4(0x80000000)
liveins: $q0, $q1, $r0, $r3
renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !34
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !38
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !32
bb.4.for.cond.cleanup:
liveins: $r0, $r12
DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store (s32) into %ir.a)
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43
...
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