9cb8f4d1ad
The semantics of tail predication loops means that the value of LR as an instruction is executed determines the predicate. In other words: mov r3, #3 DLSTP lr, r3 // Start tail predication, lr==3 VADD.s32 q0, q1, q2 // Lanes 0,1 and 2 are updated in q0. mov lr, #1 VADD.s32 q0, q1, q2 // Only first lane is updated. This means that the value of lr cannot be spilled and re-used in tail predication regions without potentially altering the behaviour of the program. More lanes than required could be stored, for example, and in the case of a gather those lanes might not have been setup, leading to alignment exceptions. This patch adds a new lr predicate operand to MVE instructions in order to keep a reference to the lr that they use as a tail predicate. It will usually hold the zeroreg meaning not predicated, being set to the LR phi value in the MVETPAndVPTOptimisationsPass. This will prevent it from being spilled anywhere that it needs to be used. A lot of tests needed updating. Differential Revision: https://reviews.llvm.org/D107638
240 lines
10 KiB
YAML
240 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir --verify-machineinstrs -run-pass=finalize-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm-arm-none-eabi"
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; Function Attrs: argmemonly nofree nosync nounwind willreturn
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg)
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; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
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declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg)
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define void @test1(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
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entry:
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%0 = bitcast i32* %X to i8*
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%1 = bitcast i32* %Y to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 %n, i1 false)
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ret void
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}
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define void @test2(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
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entry:
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%cmp6 = icmp sgt i32 %n, 0
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br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%X.bits = bitcast i32* %X to i8*
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%Y.bits = bitcast i32* %Y to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %X.bits, i8* align 4 %Y.bits, i32 %n, i1 false)
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.preheader, %entry
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ret void
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}
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define void @test3(i32* nocapture %X, i8 zeroext %c, i32 %n) {
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entry:
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%0 = bitcast i32* %X to i8*
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tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 %c, i32 %n, i1 false)
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ret void
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}
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define void @test4(i8* nocapture %X, i8 zeroext %c, i32 %n) {
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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call void @llvm.memset.p0i8.i32(i8* align 1 %X, i8 %c, i32 %n, i1 false)
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.preheader, %entry
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ret void
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}
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...
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---
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name: test1
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $r0, $r1, $r2
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; CHECK-LABEL: name: test1
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
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; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr
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; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
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; CHECK: .1:
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; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %7, %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %9, %bb.1
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; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %11, %bb.1
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; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %13, %bb.1
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; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
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; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: .2.entry:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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%2:rgpr = COPY $r2
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%1:rgpr = COPY $r1
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%0:rgpr = COPY $r0
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MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr
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tBX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test2
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
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; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1.for.body.preheader:
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
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; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr
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; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %7, %bb.3
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; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %9, %bb.3
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; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %11, %bb.3
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; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %13, %bb.3
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; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
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; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr
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; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
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; CHECK: bb.4.for.body.preheader:
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.2.for.cond.cleanup:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $r0, $r1, $r2
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%2:rgpr = COPY $r2
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%1:rgpr = COPY $r1
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%0:rgpr = COPY $r0
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t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
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t2B %bb.1, 14 /* CC::al */, $noreg
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bb.1.for.body.preheader:
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successors: %bb.2(0x80000000)
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MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr
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bb.2.for.cond.cleanup:
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tBX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test3
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $r0, $r1, $r2
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; CHECK-LABEL: name: test3
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
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; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr
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; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
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; CHECK: .1:
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; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %7, %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %9, %bb.1
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; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %11, %bb.1
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; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1
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; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: .2.entry:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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%2:rgpr = COPY $r2
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%1:mqpr = COPY $r1
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%0:rgpr = COPY $r0
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MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr
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tBX_RET 14 /* CC::al */, $noreg
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...
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---
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name: test4
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alignment: 2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test4
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
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; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
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; CHECK: bb.1.for.body.preheader:
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
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; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr
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; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %7, %bb.3
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; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %9, %bb.3
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; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %11, %bb.3
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; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
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; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1
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; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr
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; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
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; CHECK: bb.4.for.body.preheader:
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.2.for.cond.cleanup:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $r0, $r1, $r2
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%2:rgpr = COPY $r2
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%1:mqpr = COPY $r1
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%0:rgpr = COPY $r0
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t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
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t2B %bb.1, 14 /* CC::al */, $noreg
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bb.1.for.body.preheader:
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MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr
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bb.2.for.cond.cleanup:
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tBX_RET 14 /* CC::al */, $noreg
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...
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