c41b16c26b
This aligns the printer with the parser contract: the operation isn't part of the user-controllable part of the syntax. Differential Revision: https://reviews.llvm.org/D108804
363 lines
14 KiB
C++
363 lines
14 KiB
C++
//===- NVVMDialect.cpp - NVVM IR Ops and Dialect registration -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the types and operation details for the NVVM IR dialect in
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// MLIR, and the LLVM IR dialect. It also registers the dialect.
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//
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// The NVVM dialect only contains GPU specific additions on top of the general
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// LLVM dialect.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/IR/OperationSupport.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/SourceMgr.h"
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using namespace mlir;
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using namespace NVVM;
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#include "mlir/Dialect/LLVMIR/NVVMOpsDialect.cpp.inc"
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//===----------------------------------------------------------------------===//
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// Printing/parsing for NVVM ops
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//===----------------------------------------------------------------------===//
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static void printNVVMIntrinsicOp(OpAsmPrinter &p, Operation *op) {
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p << " " << op->getOperands();
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if (op->getNumResults() > 0)
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p << " : " << op->getResultTypes();
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}
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// <operation> ::=
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// `llvm.nvvm.shfl.sync.bfly %dst, %val, %offset, %clamp_and_mask`
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// ({return_value_and_is_valid})? : result_type
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static ParseResult parseNVVMShflSyncBflyOp(OpAsmParser &parser,
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OperationState &result) {
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type resultType;
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if (parser.parseOperandList(ops) ||
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parser.parseOptionalAttrDict(result.attributes) ||
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parser.parseColonType(resultType) ||
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parser.addTypeToList(resultType, result.types))
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return failure();
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for (auto &attr : result.attributes) {
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if (attr.first != "return_value_and_is_valid")
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continue;
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auto structType = resultType.dyn_cast<LLVM::LLVMStructType>();
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if (structType && !structType.getBody().empty())
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resultType = structType.getBody()[0];
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break;
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}
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auto int32Ty = IntegerType::get(parser.getBuilder().getContext(), 32);
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return parser.resolveOperands(ops, {int32Ty, resultType, int32Ty, int32Ty},
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parser.getNameLoc(), result.operands);
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}
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// <operation> ::= `llvm.nvvm.vote.ballot.sync %mask, %pred` : result_type
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static ParseResult parseNVVMVoteBallotOp(OpAsmParser &parser,
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OperationState &result) {
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MLIRContext *context = parser.getBuilder().getContext();
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auto int32Ty = IntegerType::get(context, 32);
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auto int1Ty = IntegerType::get(context, 1);
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type type;
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return failure(parser.parseOperandList(ops) ||
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parser.parseOptionalAttrDict(result.attributes) ||
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parser.parseColonType(type) ||
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parser.addTypeToList(type, result.types) ||
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parser.resolveOperands(ops, {int32Ty, int1Ty},
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parser.getNameLoc(), result.operands));
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}
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static LogicalResult verify(MmaOp op) {
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MLIRContext *context = op.getContext();
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auto f16Ty = Float16Type::get(context);
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auto f16x2Ty = LLVM::getFixedVectorType(f16Ty, 2);
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auto f32Ty = Float32Type::get(context);
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auto f16x2x4StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
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auto f32x8StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty});
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SmallVector<Type, 12> operandTypes(op.getOperandTypes().begin(),
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op.getOperandTypes().end());
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if (operandTypes != SmallVector<Type, 8>(8, f16x2Ty) &&
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operandTypes != SmallVector<Type, 12>{f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty}) {
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return op.emitOpError(
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"expected operands to be 4 <halfx2>s followed by either "
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"4 <halfx2>s or 8 floats");
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}
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if (op.getType() != f32x8StructTy && op.getType() != f16x2x4StructTy) {
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return op.emitOpError("expected result type to be a struct of either 4 "
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"<halfx2>s or 8 floats");
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}
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auto alayout = op->getAttrOfType<StringAttr>("alayout");
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auto blayout = op->getAttrOfType<StringAttr>("blayout");
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if (!(alayout && blayout) ||
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!(alayout.getValue() == "row" || alayout.getValue() == "col") ||
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!(blayout.getValue() == "row" || blayout.getValue() == "col")) {
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return op.emitOpError(
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"alayout and blayout attributes must be set to either "
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"\"row\" or \"col\"");
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}
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if (operandTypes == SmallVector<Type, 12>{f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty} &&
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op.getType() == f32x8StructTy && alayout.getValue() == "row" &&
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blayout.getValue() == "col") {
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return success();
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}
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return op.emitOpError("unimplemented mma.sync variant");
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}
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template <typename T>
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static LogicalResult verifyWMMALoadOp(T op, StringRef operand) {
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MLIRContext *context = op.getContext();
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auto i32Ty = IntegerType::get(context, 32);
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auto i32Ptr1Ty = LLVM::LLVMPointerType::get(i32Ty, 1);
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auto i32Ptr3Ty = LLVM::LLVMPointerType::get(i32Ty, 3);
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auto i32Ptr0Ty = LLVM::LLVMPointerType::get(i32Ty, 0);
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auto f16Ty = FloatType::getF16(context);
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auto f32Ty = FloatType::getF32(context);
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auto f16x2Ty = VectorType::get(2, f16Ty);
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auto f16x2x4StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
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auto f16x2x8StructTy = LLVM::LLVMStructType::getLiteral(
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context,
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{f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
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auto f32x8StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty});
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SmallVector<Type, 2> operandTypes(op.getOperandTypes().begin(),
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op.getOperandTypes().end());
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if (operandTypes != SmallVector<Type, 2>{i32Ptr1Ty, i32Ty} &&
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operandTypes != SmallVector<Type, 2>{i32Ptr3Ty, i32Ty} &&
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operandTypes != SmallVector<Type, 2>{i32Ptr0Ty, i32Ty}) {
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return op.emitOpError("expected operands to be a source pointer in memory "
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"space 0, 1, 3 followed by ldm of the source");
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}
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if (operand.equals("AOp") || operand.equals("BOp")) {
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if (op.getType() != f16x2x8StructTy) {
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return op.emitOpError("expected result type of loadAOp and loadBOp to be "
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"a struct of 8 <halfx2>s");
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}
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} else if (operand.equals("COp")) {
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if (op.getType() != f16x2x4StructTy && op.getType() != f32x8StructTy) {
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return op.emitOpError("expected result type of loadCOp to be a struct of "
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"4 <halfx2>s or 8 f32s");
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}
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}
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return success();
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}
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static LogicalResult verify(WMMALoadAM16N16K16Op op) {
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return verifyWMMALoadOp(op, "AOp");
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}
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static LogicalResult verify(WMMALoadBM16N16K16Op op) {
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return verifyWMMALoadOp(op, "BOp");
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}
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static LogicalResult verify(WMMALoadCF16M16N16K16Op op) {
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return verifyWMMALoadOp(op, "COp");
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}
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static LogicalResult verify(WMMALoadCF32M16N16K16Op op) {
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return verifyWMMALoadOp(op, "COp");
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}
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template <typename T>
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static bool verifyWMMAStoreOp(T op, SmallVector<Type> &containedElems) {
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SmallVector<Type> operandTypes(op.getOperandTypes().begin(),
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op.getOperandTypes().end());
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if (operandTypes == containedElems)
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return true;
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return false;
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}
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static LogicalResult verify(WMMAStoreF16M16N16K16Op op) {
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MLIRContext *context = op.getContext();
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auto i32Ty = IntegerType::get(context, 32);
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auto i32Ptr1Ty = LLVM::LLVMPointerType::get(i32Ty, 1);
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auto i32Ptr3Ty = LLVM::LLVMPointerType::get(i32Ty, 3);
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auto i32Ptr0Ty = LLVM::LLVMPointerType::get(i32Ty, 0);
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auto f16Ty = FloatType::getF16(context);
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auto f16x2Ty = VectorType::get(2, f16Ty);
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SmallVector<Type> type1{i32Ptr1Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, i32Ty};
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SmallVector<Type> type0{i32Ptr0Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, i32Ty};
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SmallVector<Type> type3{i32Ptr3Ty, f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty, i32Ty};
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if (verifyWMMAStoreOp(op, type1) || verifyWMMAStoreOp(op, type0) ||
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verifyWMMAStoreOp(op, type3))
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return success();
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return op.emitOpError("expected operands to be a source pointer in memory"
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"space 0, 1, 3 followed by ldm of the source");
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}
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static LogicalResult verify(WMMAStoreF32M16N16K16Op op) {
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MLIRContext *context = op.getContext();
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auto i32Ty = IntegerType::get(context, 32);
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auto i32Ptr1Ty = LLVM::LLVMPointerType::get(i32Ty, 1);
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auto i32Ptr3Ty = LLVM::LLVMPointerType::get(i32Ty, 3);
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auto i32Ptr0Ty = LLVM::LLVMPointerType::get(i32Ty, 0);
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auto f32Ty = FloatType::getF32(context);
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SmallVector<Type> type1{i32Ptr1Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, i32Ty};
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SmallVector<Type> type0{i32Ptr0Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, i32Ty};
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SmallVector<Type> type3{i32Ptr3Ty, f32Ty, f32Ty, f32Ty, f32Ty,
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f32Ty, f32Ty, f32Ty, f32Ty, i32Ty};
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if (verifyWMMAStoreOp(op, type0) || verifyWMMAStoreOp(op, type1) ||
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verifyWMMAStoreOp(op, type3))
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return success();
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return op.emitOpError("expected operands to be a source pointer in memory"
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"space 0, 1, 3 followed by ldm of the source");
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}
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static LogicalResult verify(WMMAMmaF16F16M16N16K16Op op) {
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MLIRContext *context = op.getContext();
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auto f16Ty = FloatType::getF16(context);
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auto f16x2Ty = VectorType::get(2, f16Ty);
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auto f16x2x4StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
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SmallVector<Type, 2> operandTypes(op.getOperandTypes().begin(),
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op.getOperandTypes().end());
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if (operandTypes != SmallVector<Type, 20>(20, f16x2Ty))
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return op.emitOpError("expected 20 <halfx2>s as operands");
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if (op.getResult().getType() != f16x2x4StructTy)
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return op.emitOpError("expected result type to be a struct of 4 <halfx2>s");
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return success();
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}
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static LogicalResult parseWMMAMmaF16F16M16N16K16Op(OpAsmParser &parser,
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OperationState &result) {
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SmallVector<OpAsmParser::OperandType, 4> operands;
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::llvm::SMLoc operandsLoc;
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Type operandType;
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Type resType;
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operandsLoc = parser.getCurrentLocation();
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if (parser.parseOperandList(operands) ||
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parser.parseOptionalAttrDict(result.attributes) || parser.parseColon() ||
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parser.parseType(operandType) || parser.parseArrow())
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return failure();
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unsigned numOperands = operands.size();
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SmallVector<Type> operandTypes(numOperands, operandType);
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if (parser.parseType(resType))
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return failure();
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result.addTypes(resType);
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if (parser.resolveOperands(operands, operandTypes, operandsLoc,
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result.operands))
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return failure();
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return success();
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}
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static void printWMMAMmaF16F16M16N16K16Op(OpAsmPrinter &p,
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WMMAMmaF16F16M16N16K16Op &op) {
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p << ' ';
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p << op.args();
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p.printOptionalAttrDict(op->getAttrs(), {});
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p << " : ";
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p << op->getOperand(0).getType();
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p << ' ' << "->";
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p << ' ';
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p << ::llvm::ArrayRef<::mlir::Type>(op.res().getType());
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}
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static LogicalResult verify(WMMAMmaF32F32M16N16K16Op op) {
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unsigned numABOperands = 16;
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unsigned numCOperands = 8;
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MLIRContext *context = op.getContext();
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auto f16Ty = FloatType::getF16(context);
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auto f32Ty = FloatType::getF32(context);
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auto f16x2Ty = VectorType::get(2, f16Ty);
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auto f32x8StructTy = LLVM::LLVMStructType::getLiteral(
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context, {f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty});
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SmallVector<Type> abOpTypes;
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SmallVector<Type> bOpTypes;
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SmallVector<Type> cOpTypes;
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for (auto operand : op->getOperands().take_front(numABOperands)) {
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abOpTypes.push_back(operand.getType());
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}
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for (auto operand :
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op->getOperands().drop_front(numABOperands).take_front(numCOperands)) {
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cOpTypes.push_back(operand.getType());
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}
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if (abOpTypes != SmallVector<Type>(16, f16x2Ty))
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return op.emitOpError("expected 16 <halfx2>s for `a` and `b` operand");
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if (cOpTypes != SmallVector<Type>(8, f32Ty))
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return op.emitOpError("expected 8 f32s for `c` operand");
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if (op.getResult().getType() != f32x8StructTy)
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return op.emitOpError("expected result type to be a struct of 8 f32s");
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return success();
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}
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//===----------------------------------------------------------------------===//
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// NVVMDialect initialization, type parsing, and registration.
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//===----------------------------------------------------------------------===//
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// TODO: This should be the llvm.nvvm dialect once this is supported.
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void NVVMDialect::initialize() {
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addOperations<
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#define GET_OP_LIST
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#include "mlir/Dialect/LLVMIR/NVVMOps.cpp.inc"
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>();
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// Support unknown operations because not all NVVM operations are
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// registered.
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allowUnknownOperations();
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}
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LogicalResult NVVMDialect::verifyOperationAttribute(Operation *op,
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NamedAttribute attr) {
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// Kernel function attribute should be attached to functions.
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if (attr.first == NVVMDialect::getKernelFuncAttrName()) {
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if (!isa<LLVM::LLVMFuncOp>(op)) {
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return op->emitError() << "'" << NVVMDialect::getKernelFuncAttrName()
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<< "' attribute attached to unexpected op";
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}
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}
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return success();
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}
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#define GET_OP_CLASSES
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#include "mlir/Dialect/LLVMIR/NVVMOps.cpp.inc"
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