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clang-p2996/llvm/test/CodeGen/PowerPC/vec_extload.ll
Benjamin Kramer 5ea0349ef5 When lowering an inreg sext first shift left, then right arithmetically. 
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

llvm-svn: 172322
2013-01-12 19:06:44 +00:00

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