1dd0d3cf40
This patch adds a peephole to AArch64PostSelectOptimize for codegen that is caused by RegBankSelect limiting G_EXTRACT_VECTOR_ELT only to FPR registers in both the input and output registers. This can cause a generation of COPY from FPR to GPR when, for example, the output register of the G_EXTRACT_VECTOR_ELT is used in a branch condition. This was noticed when looking at codegen differences between SDAG and GI for the s1279 kernel in the TSVC benchmark.
221 lines
7.0 KiB
LLVM
221 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=aarch64-none-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; Note: these tests use stores instead of returns as the return handling for
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; vector ptrs is currently sometimes create invalid unmerge values.
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define void @vector_gep_i32(ptr %b, i32 %off, ptr %p) {
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; CHECK-LABEL: vector_gep_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add x8, x0, w1, sxtw
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; CHECK-NEXT: str x8, [x2]
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; CHECK-NEXT: ret
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entry:
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%g = getelementptr i8, ptr %b, i32 %off
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store ptr %g, ptr %p
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ret void
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}
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define void @vector_gep_i64(ptr %b, i64 %off, ptr %p) {
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; CHECK-LABEL: vector_gep_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add x8, x0, x1
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; CHECK-NEXT: str x8, [x2]
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; CHECK-NEXT: ret
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entry:
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%g = getelementptr i8, ptr %b, i64 %off
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store ptr %g, ptr %p
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ret void
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}
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define void @vector_gep_v1i32(<1 x ptr> %b, <1 x i32> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v1i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: shl d1, d1, #32
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; CHECK-SD-NEXT: ssra d0, d1, #32
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; CHECK-SD-NEXT: str d0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v1i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fmov w8, s1
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: add x8, x9, w8, sxtw
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; CHECK-GI-NEXT: str x8, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <1 x ptr> %b, <1 x i32> %off
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store <1 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v2i32(<2 x ptr> %b, <2 x i32> %off, ptr %p) {
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; CHECK-LABEL: vector_gep_v2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: saddw v0.2d, v0.2d, v1.2s
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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entry:
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%g = getelementptr i8, <2 x ptr> %b, <2 x i32> %off
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store <2 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v3i32(<3 x ptr> %b, <3 x i32> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v3i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
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; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-SD-NEXT: saddw2 v2.2d, v2.2d, v3.4s
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; CHECK-SD-NEXT: str d2, [x0, #16]
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; CHECK-SD-NEXT: saddw v0.2d, v0.2d, v3.2s
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; CHECK-SD-NEXT: str q0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v3i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: smov x8, v3.s[0]
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-GI-NEXT: smov x9, v3.s[1]
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; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-GI-NEXT: fmov d1, x8
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; CHECK-GI-NEXT: mov w8, v3.s[2]
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; CHECK-GI-NEXT: mov v1.d[1], x9
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; CHECK-GI-NEXT: fmov x9, d2
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; CHECK-GI-NEXT: add x8, x9, w8, sxtw
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; CHECK-GI-NEXT: add v0.2d, v0.2d, v1.2d
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; CHECK-GI-NEXT: str x8, [x0, #16]
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; CHECK-GI-NEXT: str q0, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <3 x ptr> %b, <3 x i32> %off
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store <3 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v4i32(<4 x ptr> %b, <4 x i32> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v4i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: saddw2 v1.2d, v1.2d, v2.4s
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; CHECK-SD-NEXT: saddw v0.2d, v0.2d, v2.2s
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; CHECK-SD-NEXT: stp q0, q1, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v4i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: saddw v0.2d, v0.2d, v2.2s
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; CHECK-GI-NEXT: saddw2 v1.2d, v1.2d, v2.4s
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; CHECK-GI-NEXT: stp q0, q1, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <4 x ptr> %b, <4 x i32> %off
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store <4 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v1i64(<1 x ptr> %b, <1 x i64> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v1i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: add d0, d0, d1
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; CHECK-SD-NEXT: str d0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v1i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fmov x8, d0
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; CHECK-GI-NEXT: fmov x9, d1
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; CHECK-GI-NEXT: add x8, x8, x9
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; CHECK-GI-NEXT: str x8, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <1 x ptr> %b, <1 x i64> %off
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store <1 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v2i64(<2 x ptr> %b, <2 x i64> %off, ptr %p) {
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; CHECK-LABEL: vector_gep_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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entry:
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%g = getelementptr i8, <2 x ptr> %b, <2 x i64> %off
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store <2 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v3i64(<3 x ptr> %b, <3 x i64> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v3i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q3
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: // kill: def $d4 killed $d4 def $q4
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; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-SD-NEXT: mov v3.d[1], v4.d[0]
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; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-SD-NEXT: add d1, d2, d5
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; CHECK-SD-NEXT: str d1, [x0, #16]
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; CHECK-SD-NEXT: add v0.2d, v0.2d, v3.2d
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; CHECK-SD-NEXT: str q0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v3i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3
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; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4
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; CHECK-GI-NEXT: fmov x8, d2
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; CHECK-GI-NEXT: fmov x9, d5
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; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
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; CHECK-GI-NEXT: add x8, x8, x9
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; CHECK-GI-NEXT: str x8, [x0, #16]
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; CHECK-GI-NEXT: add v0.2d, v0.2d, v3.2d
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; CHECK-GI-NEXT: str q0, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <3 x ptr> %b, <3 x i64> %off
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store <3 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v4i64(<4 x ptr> %b, <4 x i64> %off, ptr %p) {
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; CHECK-SD-LABEL: vector_gep_v4i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d
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; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d
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; CHECK-SD-NEXT: stp q0, q1, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: vector_gep_v4i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: add v0.2d, v0.2d, v2.2d
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; CHECK-GI-NEXT: add v1.2d, v1.2d, v3.2d
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; CHECK-GI-NEXT: stp q0, q1, [x0]
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; CHECK-GI-NEXT: ret
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entry:
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%g = getelementptr i8, <4 x ptr> %b, <4 x i64> %off
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store <4 x ptr> %g, ptr %p
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ret void
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}
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define void @vector_gep_v4i128(<2 x ptr> %b, <2 x i128> %off, ptr %p) {
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; CHECK-LABEL: vector_gep_v4i128:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: mov v1.d[1], x2
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; CHECK-NEXT: add v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: str q0, [x4]
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; CHECK-NEXT: ret
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entry:
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%g = getelementptr i8, <2 x ptr> %b, <2 x i128> %off
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store <2 x ptr> %g, ptr %p
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ret void
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}
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