Craig Topper ebe7265b14 [Mips] Fix fast isel for i16 bswap. (#103398) ...

We need to mask the SRL result to 8 bits before ORing in the SLL. This
is needed in case bits 23:16 of the input aren't zero. They will have
been shifted into bits 15:8.

We don't need to AND the result with 0xffff. It's ok if the upper 16
bits of the register are garbage.

Fixes #103035.

2024-08-16 14:54:51 -07:00

66 KiB

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