fa42e7b6bc
Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind. This makes the CPUKind enum no longer part of the API. It wasn't providing much value. It was only used to pass between the two functions. By removing it, we can remove a dependency on a tablegen generated file from the RISCVTargetParser.h file. Then we can remove a dependency from several CMakeLists.txt.
96 lines
3.1 KiB
C++
96 lines
3.1 KiB
C++
//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features
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// for RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/TargetParser/Triple.h"
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namespace llvm {
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namespace RISCV {
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enum CPUKind : unsigned {
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#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
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#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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};
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struct CPUInfo {
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StringLiteral Name;
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CPUKind Kind;
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StringLiteral DefaultMarch;
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bool isInvalid() const { return DefaultMarch.empty(); }
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bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
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};
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constexpr CPUInfo RISCVCPUInfo[] = {
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#define PROC(ENUM, NAME, DEFAULT_MARCH) \
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{NAME, CK_##ENUM, DEFAULT_MARCH},
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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};
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static CPUKind getCPUByName(StringRef CPU) {
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return llvm::StringSwitch<CPUKind>(CPU)
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#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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.Default(CK_INVALID);
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}
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bool parseCPU(StringRef CPU, bool IsRV64) {
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CPUKind Kind = getCPUByName(CPU);
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if (Kind == CK_INVALID)
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return false;
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
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CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
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#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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.Default(CK_INVALID);
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if (Kind == CK_INVALID)
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return false;
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#define TUNE_PROC(ENUM, NAME) \
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if (Kind == CK_##ENUM) \
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return true;
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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StringRef getMArchFromMcpu(StringRef CPU) {
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CPUKind Kind = getCPUByName(CPU);
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
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}
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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}
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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}
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} // namespace RISCV
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} // namespace llvm
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