7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
27 lines
855 B
LLVM
27 lines
855 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32f | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64f | FileCheck %s
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; TODO: constant pool shouldn't be necessary for RV64IF.
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define float @float_imm() nounwind {
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; CHECK-LABEL: float_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
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; CHECK-NEXT: ret
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ret float 3.14159274101257324218750
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}
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define float @float_imm_op(float %a) nounwind {
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; CHECK-LABEL: float_imm_op:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 260096
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fadd.s fa0, fa0, fa5
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; CHECK-NEXT: ret
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%1 = fadd float %a, 1.0
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ret float %1
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}
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