7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
158 lines
5.0 KiB
LLVM
158 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
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define dso_local float @flw(ptr %a) nounwind {
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; CHECKIF-LABEL: flw:
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; CHECKIF: # %bb.0:
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; CHECKIF-NEXT: flw fa5, 0(a0)
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; CHECKIF-NEXT: flw fa4, 12(a0)
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; CHECKIF-NEXT: fadd.s fa0, fa5, fa4
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; CHECKIF-NEXT: ret
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%1 = load float, ptr %a
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%2 = getelementptr float, ptr %a, i32 3
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%3 = load float, ptr %2
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; Use both loaded values in an FP op to ensure an flw is used, even for the
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; soft float ABI
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%4 = fadd float %1, %3
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ret float %4
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}
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define dso_local void @fsw(ptr %a, float %b, float %c) nounwind {
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; Use %b and %c in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; CHECKIF-LABEL: fsw:
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; CHECKIF: # %bb.0:
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; CHECKIF-NEXT: fadd.s fa5, fa0, fa1
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; CHECKIF-NEXT: fsw fa5, 0(a0)
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; CHECKIF-NEXT: fsw fa5, 32(a0)
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; CHECKIF-NEXT: ret
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%1 = fadd float %b, %c
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store float %1, ptr %a
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%2 = getelementptr float, ptr %a, i32 8
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store float %1, ptr %2
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ret void
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}
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; Check load and store to a global
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@G = dso_local global float 0.0
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define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
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; Use %a and %b in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; CHECKIF-LABEL: flw_fsw_global:
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; CHECKIF: # %bb.0:
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; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
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; CHECKIF-NEXT: lui a0, %hi(G)
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; CHECKIF-NEXT: flw fa5, %lo(G)(a0)
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; CHECKIF-NEXT: addi a1, a0, %lo(G)
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; CHECKIF-NEXT: fsw fa0, %lo(G)(a0)
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; CHECKIF-NEXT: flw fa5, 36(a1)
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; CHECKIF-NEXT: fsw fa0, 36(a1)
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; CHECKIF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = load volatile float, ptr @G
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store float %1, ptr @G
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%3 = getelementptr float, ptr @G, i32 9
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%4 = load volatile float, ptr %3
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store float %1, ptr %3
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ret float %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define dso_local float @flw_fsw_constant(float %a) nounwind {
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; RV32IF-LABEL: flw_fsw_constant:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a0, 912092
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; RV32IF-NEXT: flw fa5, -273(a0)
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; RV32IF-NEXT: fadd.s fa0, fa0, fa5
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; RV32IF-NEXT: fsw fa0, -273(a0)
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw_fsw_constant:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a0, 228023
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; RV64IF-NEXT: slli a0, a0, 2
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; RV64IF-NEXT: flw fa5, -273(a0)
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; RV64IF-NEXT: fadd.s fa0, fa0, fa5
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; RV64IF-NEXT: fsw fa0, -273(a0)
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; RV64IF-NEXT: ret
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%1 = inttoptr i32 3735928559 to ptr
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%2 = load volatile float, ptr %1
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%3 = fadd float %a, %2
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store float %3, ptr %1
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ret float %3
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}
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declare void @notdead(ptr)
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define dso_local float @flw_stack(float %a) nounwind {
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; RV32IF-LABEL: flw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fmv.s fs0, fa0
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; RV32IF-NEXT: addi a0, sp, 4
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; RV32IF-NEXT: call notdead@plt
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; RV32IF-NEXT: flw fa5, 4(sp)
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; RV32IF-NEXT: fadd.s fa0, fa5, fs0
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw_stack:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
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; RV64IF-NEXT: fmv.s fs0, fa0
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; RV64IF-NEXT: mv a0, sp
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; RV64IF-NEXT: call notdead@plt
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; RV64IF-NEXT: flw fa5, 0(sp)
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; RV64IF-NEXT: fadd.s fa0, fa5, fs0
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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%1 = alloca float, align 4
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call void @notdead(ptr %1)
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%2 = load float, ptr %1
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%3 = fadd float %2, %a ; force load in to FPR32
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ret float %3
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}
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define dso_local void @fsw_stack(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fadd.s fa5, fa0, fa1
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; RV32IF-NEXT: fsw fa5, 8(sp)
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; RV32IF-NEXT: addi a0, sp, 8
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; RV32IF-NEXT: call notdead@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsw_stack:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: fadd.s fa5, fa0, fa1
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; RV64IF-NEXT: fsw fa5, 4(sp)
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; RV64IF-NEXT: addi a0, sp, 4
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; RV64IF-NEXT: call notdead@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b ; force store from FPR32
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%2 = alloca float, align 4
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store float %1, ptr %2
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call void @notdead(ptr %2)
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ret void
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}
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