54cf69c9d5
Summary: This patch introduces a mechanism to check the code object version from the module flag, This avoids checking from command line. In case the module flag is missing, we use the current default code object version supported in the compiler. For tools whose inputs are not IR, we may need other approach (directive, for example) to check the code object version, That will be in a separate patch later. For LIT tests update, we directly add module flag if there is only a single code object version associated with all checks in one file. In cause of multiple code object version in one file, we use the "sed" method to "clone" the checks to achieve the goal. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D14313
249 lines
14 KiB
LLVM
249 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals
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; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-attributor | FileCheck -check-prefixes=CHECK,V4 %s
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; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-attributor | FileCheck -check-prefixes=CHECK,V5 %s
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declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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declare i32 @llvm.amdgcn.workitem.id.z() #0
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declare i32 @llvm.amdgcn.lds.kernel.id() #0
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declare i64 @llvm.amdgcn.dispatch.id() #0
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declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
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declare ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
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declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0
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; Avoid adding all of these to the output attribute sets
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define void @use_everything_else() {
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; CHECK-LABEL: define {{[^@]+}}@use_everything_else
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; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
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; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
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; CHECK-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()
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; CHECK-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
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; CHECK-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
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; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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; CHECK-NEXT: [[QUEUE_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
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; CHECK-NEXT: [[VAL6:%.*]] = load volatile ptr, ptr addrspace(4) [[DISPATCH_PTR]], align 8
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; CHECK-NEXT: [[VAL7:%.*]] = load volatile ptr, ptr addrspace(4) [[QUEUE_PTR]], align 8
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; CHECK-NEXT: [[VAL8:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
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; CHECK-NEXT: store volatile i32 [[VAL8]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: [[VAL9:%.*]] = call i64 @llvm.amdgcn.dispatch.id()
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; CHECK-NEXT: store volatile i64 [[VAL9]], ptr addrspace(1) null, align 4
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; CHECK-NEXT: ret void
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;
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%val0 = call i32 @llvm.amdgcn.workitem.id.x()
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%val1 = call i32 @llvm.amdgcn.workitem.id.y()
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%val2 = call i32 @llvm.amdgcn.workitem.id.z()
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%val3 = call i32 @llvm.amdgcn.workgroup.id.x()
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%val4 = call i32 @llvm.amdgcn.workgroup.id.y()
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%val5 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %val0, ptr addrspace(1) null
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store volatile i32 %val1, ptr addrspace(1) null
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store volatile i32 %val2, ptr addrspace(1) null
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store volatile i32 %val3, ptr addrspace(1) null
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store volatile i32 %val4, ptr addrspace(1) null
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store volatile i32 %val5, ptr addrspace(1) null
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%dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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%queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
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%val6 = load volatile ptr, ptr addrspace(4) %dispatch.ptr
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%val7 = load volatile ptr, ptr addrspace(4) %queue.ptr
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%val8 = call i32 @llvm.amdgcn.lds.kernel.id()
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store volatile i32 %val8, ptr addrspace(1) null
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%val9 = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %val9, ptr addrspace(1) null
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ret void
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}
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define amdgpu_kernel void @test_default_queue_offset_v4_0(ptr addrspace(1) %kernarg) {
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; V4-LABEL: define {{[^@]+}}@test_default_queue_offset_v4_0
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; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR2:[0-9]+]] {
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; V4-NEXT: call void @use_everything_else()
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; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32
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; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V4-NEXT: ret void
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;
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; V5-LABEL: define {{[^@]+}}@test_default_queue_offset_v4_0
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; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {
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; V5-NEXT: call void @use_everything_else()
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; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32
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; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V5-NEXT: ret void
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;
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call void @use_everything_else()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 32
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%load = load ptr, ptr addrspace(4) %gep
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store ptr %load, ptr addrspace(1) %kernarg
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ret void
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}
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define amdgpu_kernel void @test_default_queue_offset_v5_0(ptr addrspace(1) %kernarg) {
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; V4-LABEL: define {{[^@]+}}@test_default_queue_offset_v5_0
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; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3:[0-9]+]] {
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; V4-NEXT: call void @use_everything_else()
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; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104
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; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V4-NEXT: ret void
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;
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; V5-LABEL: define {{[^@]+}}@test_default_queue_offset_v5_0
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; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR2:[0-9]+]] {
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; V5-NEXT: call void @use_everything_else()
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; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104
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; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V5-NEXT: ret void
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;
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call void @use_everything_else()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 104
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%load = load ptr, ptr addrspace(4) %gep
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store ptr %load, ptr addrspace(1) %kernarg
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ret void
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}
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define amdgpu_kernel void @test_completion_action_offset_v4_0(ptr addrspace(1) %kernarg) {
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; V4-LABEL: define {{[^@]+}}@test_completion_action_offset_v4_0
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; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR4:[0-9]+]] {
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; V4-NEXT: call void @use_everything_else()
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; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 40
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; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V4-NEXT: ret void
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;
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; V5-LABEL: define {{[^@]+}}@test_completion_action_offset_v4_0
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; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {
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; V5-NEXT: call void @use_everything_else()
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; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 40
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; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; V5-NEXT: ret void
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;
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call void @use_everything_else()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 40
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%load = load ptr, ptr addrspace(4) %gep
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store ptr %load, ptr addrspace(1) %kernarg
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ret void
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}
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define amdgpu_kernel void @test_completion_action_offset_v5_0(ptr addrspace(1) %kernarg) {
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; CHECK-LABEL: define {{[^@]+}}@test_completion_action_offset_v5_0
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; CHECK-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3:[0-9]+]] {
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; CHECK-NEXT: call void @use_everything_else()
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; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 112
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; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8
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; CHECK-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8
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; CHECK-NEXT: ret void
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;
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call void @use_everything_else()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 112
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%load = load ptr, ptr addrspace(4) %gep
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store ptr %load, ptr addrspace(1) %kernarg
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ret void
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}
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define amdgpu_kernel void @test_default_queue_completion_action_offset_v3_0(ptr addrspace(1) %kernarg) {
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; V4-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v3_0
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; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR5:[0-9]+]] {
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; V4-NEXT: call void @use_everything_else()
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; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32
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; V4-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16
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; V4-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16
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; V4-NEXT: ret void
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;
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; V5-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v3_0
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; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {
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; V5-NEXT: call void @use_everything_else()
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; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32
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; V5-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16
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; V5-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16
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; V5-NEXT: ret void
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;
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call void @use_everything_else()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 32
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%load = load <2 x ptr>, ptr addrspace(4) %gep
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store <2 x ptr> %load, ptr addrspace(1) %kernarg
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ret void
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}
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define amdgpu_kernel void @test_default_queue_completion_action_offset_v5_0(ptr addrspace(1) %kernarg) {
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; V4-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v5_0
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; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3]] {
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; V4-NEXT: call void @use_everything_else()
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; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104
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; V4-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16
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; V4-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16
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; V4-NEXT: ret void
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;
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; V5-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v5_0
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; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR4:[0-9]+]] {
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; V5-NEXT: call void @use_everything_else()
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; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104
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; V5-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16
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; V5-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16
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; V5-NEXT: ret void
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;
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call void @use_everything_else()%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 104
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%load = load <2 x ptr>, ptr addrspace(4) %gep
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store <2 x ptr> %load, ptr addrspace(1) %kernarg
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ret void
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}
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdgpu_code_object_version", i32 CODE_OBJECT_VERSION}
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;.
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; V4: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; V4: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V4: attributes #[[ATTR2]] = { "amdgpu-no-completion-action" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V4: attributes #[[ATTR3]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V4: attributes #[[ATTR4]] = { "amdgpu-no-default-queue" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V4: attributes #[[ATTR5]] = { "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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;.
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; V5: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; V5: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V5: attributes #[[ATTR2]] = { "amdgpu-no-completion-action" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V5: attributes #[[ATTR3]] = { "amdgpu-no-default-queue" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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; V5: attributes #[[ATTR4]] = { "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }
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;.
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; V4: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 400}
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;.
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; V5: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 500}
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;.
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