6d648e69c0
This patch enables passing non variadic vector type parameters on the caller and callee side and vector return on AIX that are passed in vector registers only. So far, support is enabled for only the AIX extended Altivec ABI Calling convention. Reviewed By: sfertile, DiggerLin Differential Revision: https://reviews.llvm.org/D86476
28 lines
1.2 KiB
LLVM
28 lines
1.2 KiB
LLVM
; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff 2>&1 | \
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; RUN: FileCheck %s --check-prefix=AIX-ERROR
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; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff 2>&1 | \
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; RUN: FileCheck %s --check-prefix=AIX-ERROR
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define dso_local <4 x i32> @vec_callee_stack(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12, <4 x i32> %vec13, <4 x i32> %vec14) {
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entry:
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%add = add <4 x i32> %vec1, %vec2
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%add1 = add <4 x i32> %add, %vec3
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%add2 = add <4 x i32> %add1, %vec4
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%add3 = add <4 x i32> %add2, %vec5
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%add4 = add <4 x i32> %add3, %vec6
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%add5 = add <4 x i32> %add4, %vec7
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%add6 = add <4 x i32> %add5, %vec8
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%add7 = add <4 x i32> %add6, %vec9
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%add8 = add <4 x i32> %add7, %vec10
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%add9 = add <4 x i32> %add8, %vec11
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%add10 = add <4 x i32> %add9, %vec12
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%add11 = add <4 x i32> %add10, %vec13
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%add12 = add <4 x i32> %add11, %vec14
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ret <4 x i32> %add12
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}
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; AIX-ERROR: LLVM ERROR: passing vector parameters to the stack is unimplemented for AIX
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