This supports bitcode compilation using `clang -fwasm-exceptions`. --- The current situation: Currently the backend requires two options for Wasm EH: `-wasm-enable-eh` and `-exception-model=wasm`. Wasm SjLj requires two options as well: `-wasm-enable-sjlj` and `-exception-model=wasm`. When using Wasm EH via Emscripten, you only need to pass `-fwasm-exceptions`, and these options will be added within the clang driver. This description will focus on the case of Wasm EH going forward, but Wasm SjLj's case is similar. When you pass `-fwasm-exceptions` to emcc and clang driver, the clang driver adds these options to the command line that calls the clang frontend (`clang -cc1`): `-mllvm -wasm-enable-eh` and `-exception-model=wasm`. `-wasm-enable-eh` is prefixed with `-mllvm`, so it is passed as is to the backend. But `-exception-model` is parsed and processed within the clang frontend and stored in `LangOptions` class. This info is later transferred to `TargetOptions` class, and then eventually passed to `MCAsmInfo` class. All LLVM code queries this `MCAsmInfo` to get the exception model. --- Problem: The problem is the whole `LangOptions` processing is bypassed when compiling bitcode, so the information transfer of `LangOptions` -> `TargetOptions` -> `MCAsmInfo` does not happen. They are all set to `ExceptionHandling::None`, which is the default value. --- What other targets do, and why we can't do the same: Other targets support bitcode compilation by the clang driver, but they can do that by using different triples. For example, X86 target supports multiple triples, each of which has its own subclass of `MCAsmInfo`, so it can hardcode the appropriate exception model within those subclasses' constructors. But we don't have separate triples for each exception mode: none, emscripten, and wasm. --- What this CL does: If we can figure out whether `-wasm-enable-eh` is passed to the backend, we can programatically set the exception model from the backend, rather than requiring it to be passed. So we check `WasmEnableEH` and `WasmEnableSjLj` variables, which are `cl::opt` for `-wasm-enable-eh` and `-wasm-enable-sjlj`, in `WebAssemblyMCAsmInfo` constructor, and if either of them is set, we set `MCAsmInfo.ExceptionType` to Wasm. `TargetOptions` cannot be updated there, so we make sure they are the same later. Fixes https://github.com/emscripten-core/emscripten/issues/15712. Reviewed By: dschuff Differential Revision: https://reviews.llvm.org/D115893
353 lines
13 KiB
C++
353 lines
13 KiB
C++
// WebAssemblyMCInstLower.cpp - Convert WebAssembly MachineInstr to an MCInst //
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains code to lower WebAssembly MachineInstrs to their
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/// corresponding MCInst records.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyMCInstLower.h"
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#include "TargetInfo/WebAssemblyTargetInfo.h"
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#include "Utils/WebAssemblyTypeUtilities.h"
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#include "Utils/WebAssemblyUtilities.h"
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#include "WebAssemblyAsmPrinter.h"
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#include "WebAssemblyISelLowering.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbolWasm.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// This disables the removal of registers when lowering into MC, as required
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// by some current tests.
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cl::opt<bool>
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WasmKeepRegisters("wasm-keep-registers", cl::Hidden,
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cl::desc("WebAssembly: output stack registers in"
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" instruction output for test purposes only."),
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cl::init(false));
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static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
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MCSymbol *
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WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
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const GlobalValue *Global = MO.getGlobal();
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if (!isa<Function>(Global)) {
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auto *WasmSym = cast<MCSymbolWasm>(Printer.getSymbol(Global));
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// If the symbol doesn't have an explicit WasmSymbolType yet and the
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// GlobalValue is actually a WebAssembly global, then ensure the symbol is a
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// WASM_SYMBOL_TYPE_GLOBAL.
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if (WebAssembly::isWasmVarAddressSpace(Global->getAddressSpace()) &&
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!WasmSym->getType()) {
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const MachineFunction &MF = *MO.getParent()->getParent()->getParent();
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const TargetMachine &TM = MF.getTarget();
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const Function &CurrentFunc = MF.getFunction();
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Type *GlobalVT = Global->getValueType();
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SmallVector<MVT, 1> VTs;
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computeLegalValueVTs(CurrentFunc, TM, GlobalVT, VTs);
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// Tables are represented as Arrays in LLVM IR therefore
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// they reach this point as aggregate Array types with an element type
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// that is a reference type.
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wasm::ValType Type;
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bool IsTable = false;
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if (GlobalVT->isArrayTy() &&
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WebAssembly::isRefType(GlobalVT->getArrayElementType())) {
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MVT VT;
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IsTable = true;
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switch (GlobalVT->getArrayElementType()->getPointerAddressSpace()) {
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case WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_FUNCREF:
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VT = MVT::funcref;
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break;
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case WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_EXTERNREF:
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VT = MVT::externref;
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break;
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default:
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report_fatal_error("unhandled address space type");
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}
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Type = WebAssembly::toValType(VT);
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} else if (VTs.size() == 1) {
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Type = WebAssembly::toValType(VTs[0]);
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} else
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report_fatal_error("Aggregate globals not yet implemented");
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if (IsTable) {
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WasmSym->setType(wasm::WASM_SYMBOL_TYPE_TABLE);
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WasmSym->setTableType(Type);
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} else {
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WasmSym->setType(wasm::WASM_SYMBOL_TYPE_GLOBAL);
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WasmSym->setGlobalType(
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wasm::WasmGlobalType{uint8_t(Type), /*Mutable=*/true});
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}
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}
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return WasmSym;
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}
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const auto *FuncTy = cast<FunctionType>(Global->getValueType());
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const MachineFunction &MF = *MO.getParent()->getParent()->getParent();
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const TargetMachine &TM = MF.getTarget();
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const Function &CurrentFunc = MF.getFunction();
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SmallVector<MVT, 1> ResultMVTs;
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SmallVector<MVT, 4> ParamMVTs;
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const auto *const F = dyn_cast<Function>(Global);
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computeSignatureVTs(FuncTy, F, CurrentFunc, TM, ParamMVTs, ResultMVTs);
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auto Signature = signatureFromMVTs(ResultMVTs, ParamMVTs);
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bool InvokeDetected = false;
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auto *WasmSym = Printer.getMCSymbolForFunction(
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F, WebAssembly::WasmEnableEmEH || WebAssembly::WasmEnableEmSjLj,
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Signature.get(), InvokeDetected);
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WasmSym->setSignature(Signature.get());
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Printer.addSignature(std::move(Signature));
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WasmSym->setType(wasm::WASM_SYMBOL_TYPE_FUNCTION);
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return WasmSym;
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}
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MCSymbol *WebAssemblyMCInstLower::GetExternalSymbolSymbol(
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const MachineOperand &MO) const {
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return Printer.getOrCreateWasmSymbol(MO.getSymbolName());
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}
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MCOperand WebAssemblyMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
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MCSymbol *Sym) const {
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MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
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unsigned TargetFlags = MO.getTargetFlags();
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switch (TargetFlags) {
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case WebAssemblyII::MO_NO_FLAG:
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break;
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case WebAssemblyII::MO_GOT_TLS:
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Kind = MCSymbolRefExpr::VK_WASM_GOT_TLS;
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break;
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case WebAssemblyII::MO_GOT:
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Kind = MCSymbolRefExpr::VK_GOT;
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break;
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case WebAssemblyII::MO_MEMORY_BASE_REL:
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Kind = MCSymbolRefExpr::VK_WASM_MBREL;
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break;
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case WebAssemblyII::MO_TLS_BASE_REL:
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Kind = MCSymbolRefExpr::VK_WASM_TLSREL;
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break;
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case WebAssemblyII::MO_TABLE_BASE_REL:
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Kind = MCSymbolRefExpr::VK_WASM_TBREL;
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break;
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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}
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const MCExpr *Expr = MCSymbolRefExpr::create(Sym, Kind, Ctx);
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if (MO.getOffset() != 0) {
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const auto *WasmSym = cast<MCSymbolWasm>(Sym);
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if (TargetFlags == WebAssemblyII::MO_GOT)
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report_fatal_error("GOT symbol references do not support offsets");
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if (WasmSym->isFunction())
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report_fatal_error("Function addresses with offsets not supported");
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if (WasmSym->isGlobal())
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report_fatal_error("Global indexes with offsets not supported");
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if (WasmSym->isTag())
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report_fatal_error("Tag indexes with offsets not supported");
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if (WasmSym->isTable())
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report_fatal_error("Table indexes with offsets not supported");
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Expr = MCBinaryExpr::createAdd(
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Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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}
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return MCOperand::createExpr(Expr);
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}
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MCOperand WebAssemblyMCInstLower::lowerTypeIndexOperand(
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SmallVector<wasm::ValType, 1> &&Returns,
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SmallVector<wasm::ValType, 4> &&Params) const {
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auto Signature = std::make_unique<wasm::WasmSignature>(std::move(Returns),
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std::move(Params));
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MCSymbol *Sym = Printer.createTempSymbol("typeindex");
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auto *WasmSym = cast<MCSymbolWasm>(Sym);
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WasmSym->setSignature(Signature.get());
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Printer.addSignature(std::move(Signature));
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WasmSym->setType(wasm::WASM_SYMBOL_TYPE_FUNCTION);
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const MCExpr *Expr =
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MCSymbolRefExpr::create(WasmSym, MCSymbolRefExpr::VK_WASM_TYPEINDEX, Ctx);
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return MCOperand::createExpr(Expr);
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}
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// Return the WebAssembly type associated with the given register class.
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static wasm::ValType getType(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return wasm::ValType::I32;
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if (RC == &WebAssembly::I64RegClass)
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return wasm::ValType::I64;
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if (RC == &WebAssembly::F32RegClass)
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return wasm::ValType::F32;
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if (RC == &WebAssembly::F64RegClass)
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return wasm::ValType::F64;
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if (RC == &WebAssembly::V128RegClass)
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return wasm::ValType::V128;
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if (RC == &WebAssembly::EXTERNREFRegClass)
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return wasm::ValType::EXTERNREF;
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if (RC == &WebAssembly::FUNCREFRegClass)
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return wasm::ValType::FUNCREF;
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llvm_unreachable("Unexpected register class");
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}
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static void getFunctionReturns(const MachineInstr *MI,
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SmallVectorImpl<wasm::ValType> &Returns) {
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const Function &F = MI->getMF()->getFunction();
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const TargetMachine &TM = MI->getMF()->getTarget();
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Type *RetTy = F.getReturnType();
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SmallVector<MVT, 4> CallerRetTys;
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computeLegalValueVTs(F, TM, RetTy, CallerRetTys);
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valTypesFromMVTs(CallerRetTys, Returns);
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}
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void WebAssemblyMCInstLower::lower(const MachineInstr *MI,
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MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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const MCInstrDesc &Desc = MI->getDesc();
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unsigned NumVariadicDefs = MI->getNumExplicitDefs() - Desc.getNumDefs();
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI->getOperand(I);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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MI->print(errs());
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_MachineBasicBlock:
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MI->print(errs());
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llvm_unreachable("MachineBasicBlock operand should have been rewritten");
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case MachineOperand::MO_Register: {
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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continue;
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const WebAssemblyFunctionInfo &MFI =
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*MI->getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
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unsigned WAReg = MFI.getWAReg(MO.getReg());
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MCOp = MCOperand::createReg(WAReg);
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break;
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}
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case MachineOperand::MO_Immediate: {
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unsigned DescIndex = I - NumVariadicDefs;
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if (DescIndex < Desc.NumOperands) {
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const MCOperandInfo &Info = Desc.OpInfo[DescIndex];
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if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) {
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SmallVector<wasm::ValType, 4> Returns;
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SmallVector<wasm::ValType, 4> Params;
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const MachineRegisterInfo &MRI =
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MI->getParent()->getParent()->getRegInfo();
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for (const MachineOperand &MO : MI->defs())
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Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
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for (const MachineOperand &MO : MI->explicit_uses())
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if (MO.isReg())
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Params.push_back(getType(MRI.getRegClass(MO.getReg())));
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// call_indirect instructions have a callee operand at the end which
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// doesn't count as a param.
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if (WebAssembly::isCallIndirect(MI->getOpcode()))
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Params.pop_back();
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// return_call_indirect instructions have the return type of the
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// caller
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if (MI->getOpcode() == WebAssembly::RET_CALL_INDIRECT)
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getFunctionReturns(MI, Returns);
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MCOp = lowerTypeIndexOperand(std::move(Returns), std::move(Params));
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break;
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} else if (Info.OperandType == WebAssembly::OPERAND_SIGNATURE) {
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auto BT = static_cast<WebAssembly::BlockType>(MO.getImm());
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assert(BT != WebAssembly::BlockType::Invalid);
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if (BT == WebAssembly::BlockType::Multivalue) {
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SmallVector<wasm::ValType, 1> Returns;
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getFunctionReturns(MI, Returns);
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MCOp = lowerTypeIndexOperand(std::move(Returns),
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SmallVector<wasm::ValType, 4>());
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break;
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}
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}
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}
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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}
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case MachineOperand::MO_FPImmediate: {
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const ConstantFP *Imm = MO.getFPImm();
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const uint64_t BitPattern =
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Imm->getValueAPF().bitcastToAPInt().getZExtValue();
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if (Imm->getType()->isFloatTy())
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MCOp = MCOperand::createSFPImm(static_cast<uint32_t>(BitPattern));
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else if (Imm->getType()->isDoubleTy())
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MCOp = MCOperand::createDFPImm(BitPattern);
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else
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llvm_unreachable("unknown floating point immediate type");
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break;
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}
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
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break;
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case MachineOperand::MO_MCSymbol:
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assert(MO.getTargetFlags() == 0 &&
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"WebAssembly does not use target flags on MCSymbol");
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MCOp = lowerSymbolOperand(MO, MO.getMCSymbol());
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break;
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}
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OutMI.addOperand(MCOp);
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}
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if (!WasmKeepRegisters)
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removeRegisterOperands(MI, OutMI);
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else if (Desc.variadicOpsAreDefs())
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OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs()));
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}
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static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) {
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// Remove all uses of stackified registers to bring the instruction format
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// into its final stack form used thruout MC, and transition opcodes to
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// their _S variant.
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// We do this separate from the above code that still may need these
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// registers for e.g. call_indirect signatures.
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// See comments in lib/Target/WebAssembly/WebAssemblyInstrFormats.td for
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// details.
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// TODO: the code above creates new registers which are then removed here.
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// That code could be slightly simplified by not doing that, though maybe
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// it is simpler conceptually to keep the code above in "register mode"
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// until this transition point.
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// FIXME: we are not processing inline assembly, which contains register
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// operands, because it is used by later target generic code.
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if (MI->isDebugInstr() || MI->isLabel() || MI->isInlineAsm())
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return;
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// Transform to _S instruction.
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auto RegOpcode = OutMI.getOpcode();
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auto StackOpcode = WebAssembly::getStackOpcode(RegOpcode);
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assert(StackOpcode != -1 && "Failed to stackify instruction");
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OutMI.setOpcode(StackOpcode);
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// Remove register operands.
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for (auto I = OutMI.getNumOperands(); I; --I) {
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auto &MO = OutMI.getOperand(I - 1);
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if (MO.isReg()) {
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OutMI.erase(&MO);
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}
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}
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}
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