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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper ec4dd862bf [RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics. 
The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing
the immediate. To prevent his we had special patterns that provided
alternate lowering for the 0 cases. This relied on tablegen prioritizing
the 0 pattern over the sim5_plus1 range.

This patch introduces simm5_plus1_nonzero that excludes 0. It also
excludes the special case for vmsltu.vi since we can just use
vmsltu.vx and let the 0 be selected to X0.

This is an alternative to some of the changes in D116584.

Reviewed By: Chenbing.Zheng, asb

Differential Revision: https://reviews.llvm.org/D116723
2022-01-06 08:27:27 -08:00
..
GlobalISel
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
intrinsics
…
rvv
[RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics.
2022-01-06 08:27:27 -08:00
add-before-shl.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
add-imm.ll
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
addrspacecast.ll
…
aext-to-sext.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
align-loops.ll
…
align.ll
…
alloca.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
alu8.ll
[LegalizeIntegerTypes][RISCV] Teach PromoteSetCCOperands to check sign bits of unsigned compares.
2022-01-04 12:38:47 -08:00
alu16.ll
[LegalizeIntegerTypes][RISCV] Teach PromoteSetCCOperands to check sign bits of unsigned compares.
2022-01-04 12:38:47 -08:00
alu32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
alu64.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
analyze-branch.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
atomic-rmw.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
atomic-signext.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
attributes.ll
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
blockaddress.ll
…
branch-relaxation.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
branch.ll
…
bswap-ctlz-cttz-ctpop.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
byval.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
callee-saved-fpr64s.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
callee-saved-gprs.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-half.ll
[RISCV] Revert Zfhmin related changes that aren't tested and depend on f16 being a legal type.
2021-12-16 08:55:28 -08:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-lp64.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
…
calls.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
compress-float.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
compress-inline-asm.ll
…
compress.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
copy-frameindex.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
copysign-casts.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
disable-tail-calls.ll
…
disjoint.ll
…
div-by-constant.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
div.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
double-arith-strict.ll
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
2021-12-14 10:50:55 -08:00
double-arith.ll
[RISCV] Reduce duplicate FP test cases.
2021-12-09 08:33:38 -08:00
double-bitmanip-dagcombines.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
double-br-fcmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
double-calling-conv.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
double-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
double-convert.ll
[RISCV] Remove stale comments from tests. NFC
2021-12-18 13:36:03 -08:00
double-fcmp.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
double-frem.ll
[RISCV] Promote f16 frem with Zfh.
2021-11-10 17:35:07 -08:00
double-imm.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
double-intrinsics-strict.ll
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
2021-12-30 11:54:32 -08:00
double-intrinsics.ll
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
2021-12-27 14:59:23 -08:00
double-isnan.ll
…
double-mem.ll
…
double-previous-failure.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
double-select-fcmp.ll
…
double-stack-spill-restore.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
dwarf-eh.ll
…
elf-preemption.ll
…
exception-pointer-register.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fastcc-float.ll
…
fastcc-int.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fixups-diff.ll
…
fixups-relax-diff.ll
…
float-arith-strict.ll
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
2021-12-14 10:50:55 -08:00
float-arith.ll
[RISCV] Reduce duplicate FP test cases.
2021-12-09 08:33:38 -08:00
float-bit-preserving-dagcombines.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
float-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
float-convert.ll
[RISCV] Remove stale comments from tests. NFC
2021-12-18 13:36:03 -08:00
float-fcmp.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
float-frem.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
float-imm.ll
…
float-intrinsics-strict.ll
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
2021-12-30 11:54:32 -08:00
float-intrinsics.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
float-isnan.ll
…
float-mem.ll
…
float-select-fcmp.ll
…
flt-rounds.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fold-addi-loadstore.ll
…
fp16-promote.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fp128.ll
…
fp-imm.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fpclamptosat_vec.ll
[RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.
2021-12-31 17:15:20 -08:00
fpclamptosat.ll
[RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.
2021-12-31 17:15:20 -08:00
fpenv.ll
…
frame-info.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
frame.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
frameaddr-returnaddr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
frm-dependency.ll
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
2021-12-14 10:17:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
half-arith-strict.ll
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
2021-12-14 10:50:55 -08:00
half-arith.ll
[RISCV] Reduce duplicate FP test cases.
2021-12-09 08:33:38 -08:00
half-bitmanip-dagcombines.ll
[RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64.
2021-08-08 18:30:48 -07:00
half-br-fcmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
half-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
half-convert.ll
[RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.
2021-12-31 17:15:20 -08:00
half-fcmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
half-frem.ll
[RISCV] Promote f16 frem with Zfh.
2021-11-10 17:35:07 -08:00
half-imm.ll
…
half-intrinsics.ll
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
2021-12-27 14:59:23 -08:00
half-isnan.ll
…
half-mem.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
half-select-fcmp.ll
…
hoist-global-addr-base.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
i32-icmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
imm-cse.ll
…
imm.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
indirectbr.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
2021-12-23 20:32:36 -06:00
inline-asm-S-constraint.ll
…
inline-asm.ll
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
2022-01-06 08:13:42 -08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
jumptable.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
large-stack.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
legalize-fneg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
lit.local.cfg
…
live-sp.mir
[RISCV] Fix invalid kill on callee save
2021-11-02 11:56:54 +00:00
lsr-legaladdimm.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
machine-outliner-patchable.ll
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
2021-12-13 13:24:29 -08:00
machineoutliner-jumptable.mir
[RISCV] Fix Machine Outliner jump table handling.
2021-09-09 07:32:30 +02:00
machineoutliner.mir
…
MachineSink-implicit-x0.mir
Fix minor deficiency in machine-sink.
2021-11-12 08:01:13 +01:00
mattr-invalid-combination.ll
…
mem64.ll
…
mem.ll
…
mir-target-flags.ll
…
module-target-abi2.ll
…
module-target-abi.ll
…
mul.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
musttail-call.ll
…
neg-abs.ll
…
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
2021-12-23 10:48:28 +05:30
out-of-reach-emergency-slot.mir
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
overflow-intrinsic-optimizations.ll
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
2021-08-31 11:23:56 -07:00
patchable-function-entry.ll
…
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
prefetch.ll
…
readcyclecounter.ll
…
rem.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
remat.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
rv32zba.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv32zbb-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbb-zbp.ll
[RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.
2021-12-23 10:42:20 +08:00
rv32zbb.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rv32zbc-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbe-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbp-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv32zbr.ll
…
rv32zbs.ll
[RISCV] Fold (and (not (srl X, C)), 1) to (xor (bexti X, C), 1) when have Zbs extension.
2021-12-16 15:01:05 +08:00
rv32zbt.ll
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
rv64d-double-convert.ll
…
rv64f-float-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
rv64f-float-convert.ll
…
rv64i-complex-float.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rv64i-demanded-bits.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
rv64i-single-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64m-exhaustive-w-insts.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64zba.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64zbb-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbb-zbp.ll
[RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.
2021-12-23 10:42:20 +08:00
rv64zbb.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
rv64zbc-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbe-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbp-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbp.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
rv64zbr.ll
…
rv64zbs.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
rv64zbt.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zfh-half-convert-strict.ll
[RISCV] Rename two tests to reflect extension being tested. NFC
2021-12-27 14:44:34 -08:00
rv64zfh-half-convert.ll
[RISCV] Rename two tests to reflect extension being tested. NFC
2021-12-27 14:44:34 -08:00
rv64zfh-half-intrinsics-strict.ll
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
2021-12-30 11:54:32 -08:00
rv64zfh-half-intrinsics.ll
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
2021-12-27 14:59:23 -08:00
sadd_sat_plus.ll
[RISCV] Add a few more instructions to hasAllNBitUsers.
2021-12-29 09:17:47 -08:00
sadd_sat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
saverestore.ll
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scalable-vector-struct.ll
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sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll
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select-bare.ll
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select-binop-identity.ll
[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
2021-08-10 09:02:56 -07:00
select-cc.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
select-const.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
select-constant-xor.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
select-optimize-multiple.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
select-optimize-multiple.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
select-or.ll
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selectcc-to-shiftand.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
setcc-logic.ll
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
sextw-removal.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
shadowcallstack.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
shift-and.ll
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
shifts.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
shlimm-addimm.ll
[RISCV][test] Add tests of (add (shl r, c0), c1)
2021-10-14 14:53:03 +00:00
shrinkwrap.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
sink-icmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
spill-fpr-scalar.ll
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split-offsets.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
split-sp-adjust.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
srem-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
srem-seteq-illegal-types.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
srem-vector-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
ssub_sat_plus.ll
[RISCV] Add a few more instructions to hasAllNBitUsers.
2021-12-29 09:17:47 -08:00
ssub_sat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
stack-realignment.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
stack-slot-size.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
stack-store-check.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
subtarget-features-std-ext.ll
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tail-calls.ll
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target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll
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uadd_sat_plus.ll
[RISCV] Add a few more instructions to hasAllNBitUsers.
2021-12-29 09:17:47 -08:00
uadd_sat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
umulo-128-legalisation-lowering.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
urem-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
urem-seteq-illegal-types.ll
[RISCV] Add a few more instructions to hasAllNBitUsers.
2021-12-29 09:17:47 -08:00
urem-vector-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
usub_sat_plus.ll
[RISCV] Add a few more instructions to hasAllNBitUsers.
2021-12-29 09:17:47 -08:00
usub_sat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vararg.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
vec3-setcc-crash.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vector-abi.ll
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verify-instr.mir
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wide-mem.ll
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xaluo.ll
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
zext-with-load-is-free.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
zfh-half-intrinsics-strict.ll
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
2021-12-30 11:54:32 -08:00
zfh-half-intrinsics.ll
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
2021-12-27 14:59:23 -08:00
zfh-imm.ll
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