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clang-p2996/llvm/test/CodeGen/RISCV/rvv
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Craig Topper ec4dd862bf [RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics. 
The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing
the immediate. To prevent his we had special patterns that provided
alternate lowering for the 0 cases. This relied on tablegen prioritizing
the 0 pattern over the sim5_plus1 range.

This patch introduces simm5_plus1_nonzero that excludes 0. It also
excludes the special case for vmsltu.vi since we can just use
vmsltu.vx and let the 0 be selected to X0.

This is an alternative to some of the changes in D116584.

Reviewed By: Chenbing.Zheng, asb

Differential Revision: https://reviews.llvm.org/D116723
2022-01-06 08:27:27 -08:00
..
abs-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
access-fixed-objects-by-rvv.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
addi-scalable-offset.mir
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
allocate-lmul-2-4-8.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
bitreverse-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
bswap-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-fastcc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
combine-sats.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
combine-splats.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
combine-store-fp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
common-shuffle-patterns.ll
[RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.
2021-12-30 17:16:18 +08:00
commuted-op-indices-regression.mir
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
constant-folding.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
ctlz-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
ctpop-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
cttz-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
debug-info-rvv-dbg-value.mir
[RISCV] Emit DWARF location expression for RVV stack objects.
2021-11-27 15:13:10 +08:00
emergency-slot.mir
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
extload-truncstore.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
extract-subvector.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
extractelt-fp-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
extractelt-fp-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
extractelt-i1.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
extractelt-int-rv32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
extractelt-int-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fceil-sdnode.ll
[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
2021-12-01 11:25:28 -08:00
ffloor-sdnode.ll
[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
2021-12-01 11:25:28 -08:00
fixed-vector-strided-load-store-negative.ll
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
fixed-vector-strided-load-store.ll
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
fixed-vectors-abs.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-bitcast-large-vector.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-bitcast.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-bitreverse.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-bswap.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-calling-conv-fastcc.ll
[PR52475] Ensure a correct chain in copies to/from hidden sret parameter
2021-12-13 10:46:32 +00:00
fixed-vectors-calling-conv.ll
[PR52475] Ensure a correct chain in copies to/from hidden sret parameter
2021-12-13 10:46:32 +00:00
fixed-vectors-ctlz.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-ctpop.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-cttz.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-elen.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-emergency-slot.mir
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
fixed-vectors-extload-truncstore.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-extract-i1.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fixed-vectors-extract-subvector.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-extract.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-fp2i.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-fp-bitcast.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-fp-buildvec.ll
[RISCV] Use vmv.s.x instead of vfmv.s.f when the floating point scalar is 0.
2021-12-30 10:16:54 +08:00
fixed-vectors-fp-conv.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-fp-setcc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-fp-shuffles.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-fp-splat.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-fp-vrgather.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-fp.ll
[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
2021-12-01 11:25:28 -08:00
fixed-vectors-i2fp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-insert-i1.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-insert-subvector.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-insert.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-int-buildvec.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-int-exttrunc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-int-setcc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-int-shuffles.ll
[RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.
2021-12-30 17:16:18 +08:00
fixed-vectors-int-splat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-int-vrgather.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-int.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-marith-vp.ll
[RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions
2021-12-23 15:02:32 -06:00
fixed-vectors-mask-buildvec.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
fixed-vectors-mask-load-store.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-mask-logic.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-mask-splat.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-gather.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-load-fp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-load-int.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-scatter.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-store-fp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-masked-store-int.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-reduction-fp-vp.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
fixed-vectors-reduction-fp.ll
[RISCV] Use positive 0.0 for the neutral element in fadd reductions if nsz is present.
2021-12-23 10:38:00 -06:00
fixed-vectors-reduction-int-vp.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
fixed-vectors-reduction-int.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
fixed-vectors-reduction-mask-vp.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
fixed-vectors-select-fp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-select-int.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
fixed-vectors-stepvector-rv32.ll
[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID
2021-07-22 09:36:12 +01:00
fixed-vectors-stepvector-rv64.ll
[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID
2021-07-22 09:36:12 +01:00
fixed-vectors-store-merge-crash.ll
[DAGCombiner][RISCV] Don't use vector types in DAGCombiner::tryStoreMergeOfLoads if we need a rotate.
2021-08-30 08:47:15 -07:00
fixed-vectors-unaligned.ll
[RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.
2021-12-30 17:16:18 +08:00
fixed-vectors-vadd-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vand-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vdivu-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vfadd-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vfdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vfmax.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
fixed-vectors-vfmin.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
fixed-vectors-vfmul-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vfsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vmul-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vnsra-vnsrl.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
fixed-vectors-vor-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vpgather.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
fixed-vectors-vpload.ll
[RISCV] Optimize vp.load with an all-ones mask
2021-11-02 17:23:39 +00:00
fixed-vectors-vpscatter.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vpstore.ll
[RISCV][VP] Mangle pointers in vp.load and vp.store tests
2021-11-02 16:46:32 +00:00
fixed-vectors-vreductions-mask.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vrem-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vremu-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vrsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vsadd.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vsaddu.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vselect-vp.ll
[LegalizeTypes][VP] Add integer promotion support for vp.select
2022-01-05 11:01:52 +00:00
fixed-vectors-vselect.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vshl-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vsra-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vsrl-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vssub.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vssubu.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixed-vectors-vwmacc.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vwmaccu.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vwmul.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vwmulu.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fixed-vectors-vxor-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
frameindex-addr.ll
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
ftrunc-sdnode.ll
[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
2021-12-01 11:25:28 -08:00
get-vlen-debugloc.mir
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
inline-asm.ll
[RISCV] Fix vm operand constraint to fit GCC's behavior
2021-12-09 14:46:49 +08:00
insert-subvector.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
insertelt-fp-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
insertelt-fp-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
insertelt-i1.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
insertelt-int-rv32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
insertelt-int-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
interleave-crash.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
large-rvv-stack-size.mir
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
legalize-load-sdnode.ll
[SelectionDAG] Replace the Chain in LOAD->VP_LOAD widening
2021-11-10 17:49:12 +00:00
legalize-scalable-vectortype.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
legalize-store-sdnode.ll
[SelectionDAG] Widen scalable-vector loads/stores via VP_LOAD/VP_STORE
2021-11-10 09:55:03 +00:00
load-add-store-8.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
load-add-store-16.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
load-add-store-32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
load-add-store-64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
load-mask.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
localvar.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
marith-vp.ll
[RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions
2021-12-23 15:02:32 -06:00
mask-exts-truncs-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
mask-exts-truncs-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
mask-reg-alloc.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
masked-load-fp.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
masked-load-int.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
masked-store-fp.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
masked-store-int.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
memory-args.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
mgather-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
mscatter-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
named-vector-shuffle-reverse.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
no-reserved-frame.ll
[RISCV] Fix a bug in RISCVFrameLowering.
2021-11-30 10:39:35 +08:00
pr52475.ll
[PR52475] Ensure a correct chain in copies to/from hidden sret parameter
2021-12-13 10:46:32 +00:00
reg-coalescing.mir
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
regalloc-fast-crash.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
rv32-spill-vector-csr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rv32-spill-vector.ll
change rvv frame layout
2021-03-13 16:05:55 +08:00
rv32-spill-zvlsseg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv32-vsetvli-intrinsics.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
rv64-spill-vector-csr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rv64-spill-vector.ll
change rvv frame layout
2021-03-13 16:05:55 +08:00
rv64-spill-zvlsseg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64-vsetvli-intrinsics.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
rvv-args-by-mem.ll
[RISCV] Support passing scalable vectur values through the stack.
2021-12-28 09:26:36 +08:00
rvv-framelayout.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rvv-out-arguments.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
rvv-vscale.i32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rvv-vscale.i64.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
saddo-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
select-fp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
select-int.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
select-sra.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
setcc-fp-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
setcc-fp-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
setcc-integer-rv32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
setcc-integer-rv64.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
sink-splat-operands.ll
[RISCV] Teach RISCVTargetLowering::shouldSinkOperands to handle udiv/sdiv/urem/srem.
2021-11-30 18:47:51 -08:00
smulo-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
stepvector.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
tail-agnostic-impdef-copy.mir
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
umulo-sdnode.ll
[AArch64][RISCV] Fix expected smulo/umulo test output
2021-11-18 11:57:26 +00:00
unaligned-loads-stores.ll
[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
2021-10-05 21:49:54 +08:00
undef-vp-ops.ll
[DAGCombiner][VP] Fold zero-length or false-masked VP ops
2021-09-27 11:30:09 +01:00
urem-seteq-vec.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vaadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vaadd-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vaaddu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vaaddu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vadc-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vadc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vadd-policy.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vadd-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vadd-sdnode.ll
[RISCV] Merge vector tests for rv32 and rv64 into a single test file
2021-10-22 09:04:30 -07:00
vadd-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vand-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vand-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vand-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vand-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vasub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vasub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vasubu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vasubu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vcompress-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vcompress-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vcpop-rv32.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vcpop-rv64.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vdiv-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vdiv-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vdiv-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
vdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vdivu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vdivu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vdivu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vdivu-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vexts-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfabs-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfadd-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfadd-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfadd-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfadd-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfclass-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfclass-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfcopysign-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfcvt-f-x-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-f-x-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-f-xu-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-f-xu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-rtz-x-f-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-rtz-x-f-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-rtz-xu-f-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-rtz-xu-f-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-x-f-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-x-f-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-xu-f-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfcvt-xu-f-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfdiv-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfdiv-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfdiv-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfirst-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfirst-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfmacc-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmadd-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmadd-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmadd-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmax-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmax-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmax-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmerge-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmerge-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmin-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmin-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmin-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmsac-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmsac-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmsub-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmsub-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmsub-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmul-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmul-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfmul-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmul-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfmv.f.s.ll
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
2021-07-23 09:12:05 -07:00
vfmv.s.f-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmv.s.f-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmv.v.f-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfmv.v.f-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfncvt-f-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-f-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-f-x-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-f-x-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-f-xu-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-f-xu-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rod-f-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rod-f-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rtz-x-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rtz-x-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rtz-xu-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-rtz-xu-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-x-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-x-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-xu-f-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfncvt-xu-f-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfneg-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmacc-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmadd-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmadd-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmadd-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmsac-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmsac-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmsub-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmsub-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfnmsub-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfpext-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfptoi-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfptrunc-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfrdiv-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrdiv-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrdiv-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfrec7-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrec7-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfredmax-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredmax-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredmin-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredmin-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredosum-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredosum-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfredusum-rv32.ll
[RISCV] Restore tests for vf(w)redusum.
2021-11-01 14:35:22 -07:00
vfredusum-rv64.ll
[RISCV] Restore tests for vf(w)redusum.
2021-11-01 14:35:22 -07:00
vfrsqrt7-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrsqrt7-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrsub-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrsub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfrsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfsgnj-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsgnj-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsgnjn-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsgnjn-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsgnjx-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsgnjx-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfslide1down-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfslide1down-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfslide1up-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfslide1up-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vfsqrt-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsqrt-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsqrt-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfsub-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vfsub-sdnode.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwadd-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwadd.w-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwadd.w-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-f-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-f-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-x-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-x-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-xu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-f-xu-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-rtz-x-f-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-rtz-x-f-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-rtz-xu-f-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-rtz-xu-f-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-x-f-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-x-f-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-xu-f-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwcvt-xu-f-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwmacc-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwmsac-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwmsac-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwmul-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwmul-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwnmacc-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwnmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwnmsac-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwnmsac-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwredosum-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwredosum-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vfwredusum-rv32.ll
[RISCV] Restore tests for vf(w)redusum.
2021-11-01 14:35:22 -07:00
vfwredusum-rv64.ll
[RISCV] Restore tests for vf(w)redusum.
2021-11-01 14:35:22 -07:00
vfwsub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwsub-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwsub.w-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vfwsub.w-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vid-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vid-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
viota-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
viota-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vitofp-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vle-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vle-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vleff-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vleff-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vlm-rv32.ll
[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
2021-10-05 21:49:54 +08:00
vlm-rv64.ll
[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
2021-10-05 21:49:54 +08:00
vloxei-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vloxei-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vloxseg-rv32.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vloxseg-rv64.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vlse-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlse-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlseg-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlseg-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlsegff-rv32-dead.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vlsegff-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlsegff-rv64-dead.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vlsegff-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlsseg-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vlsseg-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vluxei-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vluxei-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vluxseg-rv32.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vluxseg-rv64.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vmacc-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmadc-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmadc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmadc.carry.in-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmadc.carry.in-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmadd-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmadd-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmand-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmand-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmandn-rv32.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmandn-rv64.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmarith-sdnode.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmax-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmax-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmax-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmaxu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmaxu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmaxu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmclr-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmclr-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmerge-rv32.ll
[RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.
2021-10-25 09:03:59 -07:00
vmerge-rv64.ll
[RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.
2021-10-25 09:03:59 -07:00
vmfeq-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfeq-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfge-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfge-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfgt-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfgt-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfle-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfle-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmflt-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmflt-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfne-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmfne-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmin-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmin-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmin-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vminu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vminu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vminu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmnand-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmnand-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmnor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmnor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmorn-rv32.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmorn-rv64.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmsbc-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmsbc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmsbc.borrow.in-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsbc.borrow.in-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsbf-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsbf-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmseq-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmseq-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmset-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmset-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmsge-rv32.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmsge-rv64.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmsgeu-rv32.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmsgeu-rv64.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vmsgt-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsgt-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsgtu-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsgtu-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsif-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsif-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsle-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsle-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsleu-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsleu-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmslt-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmslt-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsltu-rv32.ll
[RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics.
2022-01-06 08:27:27 -08:00
vmsltu-rv64.ll
[RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics.
2022-01-06 08:27:27 -08:00
vmsne-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsne-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsof-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmsof-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vmul-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmul-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmul-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmul-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmulh-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmulh-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmulh-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmulhsu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmulhsu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmulhu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmulhu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vmulhu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmv-copy.mir
[RISCV] Convert whole register copies as the source defined explicitly.
2021-12-27 13:59:49 +08:00
vmv.s.x-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vmv.s.x-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmv.v.v-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmv.v.v-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmv.v.x-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmv.v.x-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmv.x.s-rv32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vmv.x.s-rv64.ll
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
2021-07-23 09:12:05 -07:00
vmxnor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmxnor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmxor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vmxor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vnclip-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnclip-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnclipu-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnclipu-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnmsac-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vnmsac-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vnmsub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vnmsub-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vnmsub-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vnsra-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnsra-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnsrl-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vnsrl-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vor-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vor-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vor-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vor-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vpgather-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vpload.ll
[RISCV] Optimize vp.load with an all-ones mask
2021-11-02 17:23:39 +00:00
vpscatter-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vpstore.ll
[RISCV][VP] Mangle pointers in vp.load and vp.store tests
2021-11-02 16:46:32 +00:00
vredand-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredand-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmax-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmax-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmaxu-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmaxu-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmin-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredmin-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredminu-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredminu-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredsum-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredsum-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vreductions-fp-sdnode.ll
[RISCV] Use positive 0.0 for the neutral element in fadd reductions if nsz is present.
2021-12-23 10:38:00 -06:00
vreductions-fp-vp.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
vreductions-int-rv32.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
vreductions-int-rv64.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
vreductions-int-vp.ll
[RISCV] Don't use VLMAX for start value splat in reduction lowering.
2021-12-13 09:06:42 -08:00
vreductions-mask-vp.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vreductions-mask.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vredxor-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vredxor-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vrem-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vrem-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vrem-sdnode.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
vrem-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vremu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vremu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vremu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vremu-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vrgather-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vrgather-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vrgatherei16-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vrgatherei16-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vrsub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vrsub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vrsub-sdnode.ll
[RISCV] Merge vector tests for rv32 and rv64 into a single test file
2021-10-22 09:04:30 -07:00
vrsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsadd-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsadd-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsaddu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsaddu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsaddu-sdnode.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsbc-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsbc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vse-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vse-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vselect-fp-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vselect-fp-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vselect-int-rv32.ll
[SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
2021-11-17 08:55:11 +00:00
vselect-int-rv64.ll
[SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
2021-11-17 08:55:11 +00:00
vselect-mask.ll
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vselect-vp.ll
[LegalizeTypes][VP] Add integer promotion support for vp.select
2022-01-05 11:01:52 +00:00
vsetvl-ext.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsetvli-insert-crossbb.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
vsetvli-insert-crossbb.mir
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
vsetvli-insert.ll
[RISCV] Fix incorrect cases of vmv.s.f in the VSETVLI insert pass.
2021-12-31 14:17:03 +08:00
vsetvli-insert.mir
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
vsetvli-regression.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsext-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vsext-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vshl-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vshl-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vslide1down-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vslide1down-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vslide1up-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vslide1up-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vslidedown-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vslidedown-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vslideup-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vslideup-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsll-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsll-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsm-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsm-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsmul-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsmul-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsoxei-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsoxei-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsoxseg-rv32.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vsoxseg-rv64.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vsplats-fp.ll
[RISCV] Convert (splat_vector (load)) to vlse with 0 stride.
2021-12-14 09:14:03 -08:00
vsplats-i1.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsplats-i64.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsra-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsra-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsra-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsra-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsrl-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsrl-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsrl-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsrl-vp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsse-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsse-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsseg-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsseg-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vssra-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssra-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssrl-rv32.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssrl-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssseg-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vssseg-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vssub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vssub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssub-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vssubu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vssubu-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vssubu-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsub-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vsub-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vsub-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vsuxei-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsuxei-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vsuxseg-rv32.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vsuxseg-rv64.ll
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
vtruncs-sdnode.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vwadd-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwadd-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwadd.w-rv32.ll
[RISCV] Add extra -early-live-intervals test coverage
2021-11-17 10:35:55 +00:00
vwadd.w-rv64.ll
[RISCV] Add extra -early-live-intervals test coverage
2021-11-17 10:35:55 +00:00
vwaddu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwaddu-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwaddu.w-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwaddu.w-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmacc-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmacc-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccsu-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccsu-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccu-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccu-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccus-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmaccus-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwmul-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmul-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmulsu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmulsu-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmulu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwmulu-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwredsum-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwredsum-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwredsumu-rv32.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwredsumu-rv64.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
vwsub-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsub-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsub.w-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsub.w-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsubu-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsubu-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsubu.w-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vwsubu.w-rv64.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vxor-rv32.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vxor-rv64.ll
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
vxor-sdnode.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
vxor-vp.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
vzext-rv32.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
vzext-rv64.ll
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
wrong-stack-slot-rv32.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wrong-stack-slot-rv64.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
zvlsseg-copy.mir
[RISCV] Update mir tests.
2021-09-23 09:42:16 +08:00
zvlsseg-spill.mir
Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
2021-10-02 10:44:11 -07:00
zvlsseg-zero-vl.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00