9df924a634
A new register class as well as a number of related subregisters are being added to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits long. These regsiters can also be used in consecutive pairs which leads to a register that is 2048 bits. This patch also adds 7 new instructions that use these registers. More instructions will be added in future patches. Reviewed By: amyk, saghir Differential Revision: https://reviews.llvm.org/D136366
117 lines
3.8 KiB
TableGen
117 lines
3.8 KiB
TableGen
//===-- PPCInstrFutureMMA.td - Future Instruction Set ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU for MMA.
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//
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//===----------------------------------------------------------------------===//
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class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<5> XAp;
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bits<5> XBp;
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bits<1> P;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-10} = 0;
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let Inst{11-14} = XAp{3-0};
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let Inst{15} = P;
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let Inst{16-19} = XBp{3-0};
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let Inst{20} = 0;
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let Inst{21-28} = xo;
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let Inst{29} = XAp{4};
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let Inst{30} = XBp{4};
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let Inst{31} = 0;
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}
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class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<5> XBp;
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bits<2> P;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-14} = 0;
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let Inst{15} = P{0};
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let Inst{16-19} = XBp{3-0};
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let Inst{20} = P{1};
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let Inst{21-29} = xo;
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let Inst{30} = XBp{4};
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let Inst{31} = 0;
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}
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class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I <opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<3> AB;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-10} = 0;
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let Inst{11-15} = o;
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let Inst{16-18} = AB{2-0};
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let Inst{19-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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let Predicates = [IsISAFuture] in {
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def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
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(ins wacc:$AT),
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"dmxxextfdmr512 $AT, $XAp, $XBp, 0", []> {
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let P = 0;
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}
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def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
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(ins wacc_hi:$AT),
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"dmxxextfdmr512 $AT, $XAp, $XBp, 1", []> {
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let P = 1;
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}
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def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
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(ins vsrprc:$XAp, vsrprc:$XBp),
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"dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
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let P = 0;
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}
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def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
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(ins vsrprc:$XAp, vsrprc:$XBp),
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"dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
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let P = 1;
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}
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def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
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(ins dmrrowp:$AT, u2imm:$P),
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"dmxxextfdmr256 $AT, $XBp, $P", []>;
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def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
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(ins vsrprc:$XBp, u2imm:$P),
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"dmxxinstfdmr256 $AT, $XBp, $P", []>;
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def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
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"dmmr $AT, $AB", []>;
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def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
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"dmxor $AT, $AB", []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
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"dmsetdmrz $AT", NoItinerary, []>;
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}
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