01a15dca09
Here we add a scheduling mutation in pre-ra scheduling, which will add an artificial dependency edge between mask producer and its previous nearest instruction that uses V0 register. This prevents the overlap of live intervals of mask registers and as a consequence we can reduce some spills/moves. From the test changes, we can see some improvements and also some regressions (more vtype toggles). Partially fixes #113489.
71 lines
2.7 KiB
C++
71 lines
2.7 KiB
C++
//===-- RISCVTargetMachine.h - Define TargetMachine for RISC-V --*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file declares the RISC-V specific subclass of TargetMachine.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
|
|
#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
|
|
|
|
#include "MCTargetDesc/RISCVMCTargetDesc.h"
|
|
#include "RISCVSubtarget.h"
|
|
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
|
|
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
#include <optional>
|
|
|
|
namespace llvm {
|
|
class RISCVTargetMachine : public CodeGenTargetMachineImpl {
|
|
std::unique_ptr<TargetLoweringObjectFile> TLOF;
|
|
mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
|
|
|
|
public:
|
|
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
std::optional<Reloc::Model> RM,
|
|
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
|
|
bool JIT);
|
|
|
|
const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
|
|
// DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
|
|
// subtargets are per-function entities based on the target-specific
|
|
// attributes of each function.
|
|
const RISCVSubtarget *getSubtargetImpl() const = delete;
|
|
|
|
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
|
|
|
TargetLoweringObjectFile *getObjFileLowering() const override {
|
|
return TLOF.get();
|
|
}
|
|
|
|
MachineFunctionInfo *
|
|
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
|
|
const TargetSubtargetInfo *STI) const override;
|
|
|
|
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
|
|
|
|
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override;
|
|
|
|
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
|
|
yaml::MachineFunctionInfo *
|
|
convertFuncInfoToYAML(const MachineFunction &MF) const override;
|
|
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
|
|
PerFunctionMIParsingState &PFS,
|
|
SMDiagnostic &Error,
|
|
SMRange &SourceRange) const override;
|
|
void registerPassBuilderCallbacks(PassBuilder &PB) override;
|
|
};
|
|
|
|
std::unique_ptr<ScheduleDAGMutation>
|
|
createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI);
|
|
|
|
} // namespace llvm
|
|
|
|
#endif
|