Piyou Chen 7317a6e990 [RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980) ...

For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.

This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.

2024-11-25 12:43:39 +08:00

144 KiB

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