Francis Visoiu Mistrih ae8002c1cf [X86] Preserve more liveness information in emitStackProbeInline ...

This commit fixes two issues with the liveness information after the
call:

1) The code always spills RCX and RDX if InProlog == true, which results
in an use of undefined phys reg.
2) FinalReg, JoinReg, RoundedReg, SizeReg are not added as live-ins to
the basic blocks that use them, therefore they are seen undefined.

https://llvm.org/PR38376

Differential Revision: https://reviews.llvm.org/D50020

llvm-svn: 338400

2018-07-31 16:41:12 +00:00

121 KiB

Raw Blame History

View Raw