Craig Topper e64f5d6305 [RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682) ...

ISD::VP_MERGE treats the false operand as the source for elements past
VL. The vmerge instruction encodes 3 registers and treats the vd
register as the source for the tail.

This patch adds a new ISD opcode that models the tail source explicitly.
During lowering we copy the false operand to this operand.

I think we can merge RISCVISD::VSELECT_VL with this new opcode by using
an UNDEF passthru, but I'll save that for another patch.

2023-12-21 14:34:49 -08:00

780 KiB

Raw Blame History

View Raw