d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
39 lines
766 B
YAML
39 lines
766 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that the MIR parser reports an error when an instruction
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# is missing one of its implicit register operands.
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--- |
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define i32 @foo(i32* %p) {
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entry:
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%a = load i32, i32* %p
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%0 = icmp sle i32 %a, 10
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br i1 %0, label %less, label %exit
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less:
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ret i32 0
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exit:
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ret i32 %a
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}
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...
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---
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name: foo
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body: |
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bb.0.entry:
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successors: %bb.1.less, %bb.2.exit
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$eax = MOV32rm $rdi, 1, _, 0, _
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CMP32ri8 $eax, 10, implicit-def $eflags
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; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags'
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JCC_1 %bb.2.exit, 15
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bb.1.less:
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$eax = MOV32r0 implicit-def $eflags
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bb.2.exit:
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RET64 $eax
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...
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