d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
48 lines
1.3 KiB
YAML
48 lines
1.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses stack object machine operands
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# correctly.
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--- |
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define i32 @test(i32 %a) {
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entry:
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%b = alloca i32
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%0 = alloca i32
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store i32 %a, i32* %b
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store i32 2, i32* %0
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%c = load i32, i32* %b
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ret i32 %c
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}
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...
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---
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name: test
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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frameInfo:
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maxAlignment: 4
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fixedStack:
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- { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false }
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stack:
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- { id: 0, name: b, size: 4, alignment: 4 }
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- { id: 1, size: 4, alignment: 4 }
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test
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; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg
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; CHECK: MOV32mr %stack.0.b, 1, $noreg, 0, $noreg, [[MOV32rm]]
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; CHECK: MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2
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; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, $noreg, 0, $noreg
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; CHECK: $eax = COPY [[MOV32rm1]]
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; CHECK: RET32 $eax
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%0 = MOV32rm %fixed-stack.0, 1, _, 0, _
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MOV32mr %stack.0.b, 1, _, 0, _, %0
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MOV32mi %stack.1, 1, _, 0, _, 2
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%1 = MOV32rm %stack.0, 1, _, 0, _
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$eax = COPY %1
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RET32 $eax
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...
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