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1daf2994de49d1ecba4bee4e6842aa8a564cbc96
clang-p2996/llvm/test/CodeGen/RISCV/rvv
History
Yeting Kuo 9b561ca044 [RISCV] Make performFP_TO_INTCombine fold with ISD::FRINT. (#76020) 
Fold (fp_to_int (frint X)) to (fcvt X) without rounding mode.
2023-12-21 15:03:36 +08:00
..
65704-illegal-instruction.ll
[RISCV] Move test to RVV directory. NFC
2023-12-12 17:31:59 +09:00
abs-sdnode.ll
…
abs-vp.ll
…
access-fixed-objects-by-rvv.ll
…
active_lane_mask.ll
[RISCV] Be more aggressive about shrinking constant build_vector etype (#67175)
2023-09-25 08:09:46 -07:00
addi-rvv-stack-object.mir
…
addi-scalable-offset.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
aliases.mir
…
alloca-load-store-scalable-array.ll
[IR] Enable load/store/alloca for arrays of scalable vectors.
2023-09-14 13:49:01 +00:00
alloca-load-store-scalable-struct.ll
…
allocate-lmul-2-4-8.ll
…
allone-masked-to-unmasked.ll
…
binop-splats.ll
[RISCV] Add tests where bin ops of splats could be scalarized. NFC (#65747)
2023-09-20 13:23:56 +01:00
bitreverse-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
bitreverse-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
bswap-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
bswap-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
calling-conv-fastcc.ll
…
calling-conv.ll
…
ceil-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
cmp-folds.ll
…
combine-sats.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
combine-splats.ll
…
combine-store-extract-crash.ll
[RISCV] Don't combine store of vmv.x.s/vfmv.f.s to vp_store with VL of 1 when it's indexed store (#73219)
2023-11-27 13:39:35 +08:00
combine-store.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
combine-vmv.ll
…
common-shuffle-patterns.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
commuted-op-indices-regression.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
concat-vector-insert-elt.ll
[RISCV] Add combines to form binop from tail insert idioms (#72675)
2023-11-30 07:32:42 -08:00
concat-vectors-constant-stride.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
constant-folding-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
constant-folding.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
copyprop.mir
…
cross-block-cse.ll
…
ctlz-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
ctlz-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
ctpop-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
ctpop-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
cttz-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
cttz-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
debug-info-rvv-dbg-value.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
double-round-conv.ll
[RISCV] Make performFP_TO_INTCombine fold with ISD::FRINT. (#76020)
2023-12-21 15:03:36 +08:00
emergency-slot.mir
[RISCV] Don't set KILL flag on X0 in RISCVInstrInfo::movImm.
2023-09-25 13:40:08 -07:00
expand-no-v.ll
…
extload-truncstore.ll
…
extract-subvector.ll
…
extractelt-fp.ll
…
extractelt-i1.ll
…
extractelt-int-rv32.ll
…
extractelt-int-rv64.ll
[RISCV] Use subreg extract for extract_vector_elt when vlen is known (#72666)
2023-11-27 14:33:16 -08:00
fceil-constrained-sdnode.ll
…
fceil-sdnode.ll
…
ffloor-constrained-sdnode.ll
…
ffloor-sdnode.ll
…
fixed-vectors-abs-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-abs.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-binop-splats.ll
[RISCV] Add tests where bin ops of splats could be scalarized. NFC (#65747)
2023-09-20 13:23:56 +01:00
fixed-vectors-bitcast-large-vector.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-bitcast.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-bitreverse-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-bitreverse.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-bswap-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-bswap.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-buildvec-of-binop.ll
[RISCV] Add combines to form binop from tail insert idioms (#72675)
2023-11-30 07:32:42 -08:00
fixed-vectors-calling-conv-fastcc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-calling-conv.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-ceil-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fixed-vectors-ctlz-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-ctlz.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-ctpop-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-ctpop.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-cttz-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-cttz.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-deinterleave-load.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-elen.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-emergency-slot.mir
…
fixed-vectors-extload-truncstore.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-extract-i1.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
fixed-vectors-extract-subvector.ll
[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
2023-12-15 09:26:57 -08:00
fixed-vectors-extract.ll
[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
2023-12-15 09:26:57 -08:00
fixed-vectors-fceil-constrained-sdnode.ll
…
fixed-vectors-ffloor-constrained-sdnode.ll
…
fixed-vectors-floor-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fixed-vectors-fmaximum.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-fmf.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fminimum.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-fnearbyint-constrained-sdnode.ll
…
fixed-vectors-fp2i-sat.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-fp2i.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fp-bitcast.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-buildvec.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
fixed-vectors-fp-conv.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-interleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-fp-setcc.ll
[RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866)
2023-09-27 11:00:19 +08:00
fixed-vectors-fp-shuffles.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-fp-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-vrgather.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fpext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fptosi-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptosi-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptoui-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptoui-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptrunc-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fround-costrained-sdnode.ll
…
fixed-vectors-fround.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-froundeven-constrained-sdnode.ll
…
fixed-vectors-froundeven.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fshr-fshl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-ftrunc-constrained-sdnode.ll
…
fixed-vectors-i2fp.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-insert-i1.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
fixed-vectors-insert-subvector-shuffle.ll
…
fixed-vectors-insert-subvector.ll
Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)"
2023-10-10 15:13:57 -07:00
fixed-vectors-insert.ll
[SelectionDAG] Use getVectorElementPointer in DAGCombiner::replaceStoreOfInsertLoad. (#74249)
2023-12-14 20:25:16 -08:00
fixed-vectors-int-buildvec.ll
[RISCV] Split build_vector into vreg sized pieces when exact VLEN is known (#73606)
2023-11-28 07:39:58 -08:00
fixed-vectors-int-explodevector.ll
[RISCV] Use subreg extract for extract_vector_elt when vlen is known (#72666)
2023-11-27 14:33:16 -08:00
fixed-vectors-int-exttrunc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-interleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-int-setcc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-shuffles.ll
[DAG] isSplatValue - node is a splat if all demanded elts have the same whole constant value (#74443)
2023-12-08 10:53:51 +00:00
fixed-vectors-int-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-vrgather.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int.ll
[RISCV] DAG combine (mul (add x, 1), y) -> vmadd (#71495)
2023-11-21 13:43:34 +08:00
fixed-vectors-interleave-store.ll
…
fixed-vectors-interleaved-access-zve32x.ll
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
fixed-vectors-interleaved-access.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-inttoptr-ptrtoint.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-llrint.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-load-store.ll
…
fixed-vectors-load.ll
[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
2023-12-15 09:26:57 -08:00
fixed-vectors-lrint.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-marith-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-buildvec.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-mask-load-store.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-logic.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-gather.ll
[RISCV][InsertSETVTLI] Handle large immediates in backwards walk (#75409)
2023-12-14 07:36:07 -08:00
fixed-vectors-masked-load-fp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-load-int.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-scatter.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
fixed-vectors-masked-store-fp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-masked-store-int.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-nearbyint-vp.ll
Revert "[MCP] Enhance MCP copy Instruction removal for special case (#70778)"
2023-11-27 19:39:40 +01:00
fixed-vectors-peephole-vmerge-vops.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-reduction-formation.ll
[RISCV] Allow swapped operands in reduction formation (#68634)
2023-10-23 10:37:56 -07:00
fixed-vectors-reduction-fp-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-fp.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
fixed-vectors-reduction-int-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-int.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
fixed-vectors-reduction-mask-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-rint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-round-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fixed-vectors-roundeven-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fixed-vectors-roundtozero-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fixed-vectors-segN-load.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-segN-store.ll
…
fixed-vectors-select-fp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
fixed-vectors-select-int.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-setcc-fp-vp.ll
[RISCV] Add FileCheck prefixes for test where RV32/RV64 output differs. NFC
2023-11-06 19:32:07 +08:00
fixed-vectors-setcc-int-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-setcc-int-vp.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
fixed-vectors-sext-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-sext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-shuffle-extract-subvector.ll
…
fixed-vectors-shuffle-reverse-bitrotate.ll
[RISCV] Fix crash during during i1 vector bitreverse lowering
2023-08-31 19:39:08 +01:00
fixed-vectors-shuffle-reverse.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-shuffle-rotate.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-shuffle-transpose.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-shuffle-vslide1down.ll
…
fixed-vectors-shuffle-vslide1up.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-shufflevector-vnsrl.ll
…
fixed-vectors-sitofp-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-sitofp-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-stepvector.ll
[RISCV] Be more aggressive about shrinking constant build_vector etype (#67175)
2023-09-25 08:09:46 -07:00
fixed-vectors-store-merge-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-store.ll
[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
2023-12-15 09:26:57 -08:00
fixed-vectors-strided-load-combine.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
fixed-vectors-strided-load-store-asm.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
fixed-vectors-strided-load-store-negative.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-strided-load-store.ll
[RISCV] Add gather test coverage for non-intptr index widths
2023-09-08 08:53:19 -07:00
fixed-vectors-strided-vpload.ll
[DAGCombiner] Combine vp.strided.load with unit stride to vp.load (#66766)
2023-09-19 16:39:28 +01:00
fixed-vectors-strided-vpstore.ll
[DAGCombiner] Combine vp.strided.store with unit stride to vp.store (#66774)
2023-09-19 16:43:50 +01:00
fixed-vectors-trunc-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-trunc-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-uitofp-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-uitofp-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-unaligned.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
fixed-vectors-vadd-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vadd-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vand-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vcopysign-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vdivu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfabs-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfadd-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfadd-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfclass-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfclass.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfcmp-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfcmps-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfdiv-constrained-sdnode.ll
…
fixed-vectors-vfdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfma-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vfmacc-vp.ll
…
fixed-vectors-vfmadd-constrained-sdnode.ll
…
fixed-vectors-vfmax-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmax.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmin-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmin.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmsac-vp.ll
…
fixed-vectors-vfmsub-constrained-sdnode.ll
…
fixed-vectors-vfmul-constrained-sdnode.ll
…
fixed-vectors-vfmul-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmuladd-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vfneg-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfnmacc-vp.ll
…
fixed-vectors-vfnmadd-constrained-sdnode.ll
…
fixed-vectors-vfnmsac-vp.ll
…
fixed-vectors-vfnmsub-constrained-sdnode.ll
…
fixed-vectors-vfpext-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfptoi-constrained-sdnode.ll
…
fixed-vectors-vfptrunc-constrained-sdnode.ll
[RISCV] Support STRICT_FP_ROUND and STRICT_FP_EXTEND when only have Zvfhmin (#68559)
2023-10-17 10:10:19 +08:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfsqrt-constrained-sdnode.ll
…
fixed-vectors-vfsqrt-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfsub-constrained-sdnode.ll
…
fixed-vectors-vfsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwmacc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwmul.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwsub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vitofp-constrained-sdnode.ll
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
fixed-vectors-vmacc-vp.ll
…
fixed-vectors-vmax-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmaxu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmin-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vminu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmul-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmul-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vnmsac-vp.ll
…
fixed-vectors-vnsra-vnsrl.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vor-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vpgather.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
fixed-vectors-vpload.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vpmerge.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
fixed-vectors-vpscatter.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
fixed-vectors-vpstore.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vreductions-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vrem-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vremu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vrol.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-vror.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
fixed-vectors-vrsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsaddu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vscale-range.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
fixed-vectors-vselect-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vselect.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fixed-vectors-vshl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsra-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsrl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vssub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vssubu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsub-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vw-web-simplification.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwaddu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmacc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccsu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccus.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmul.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmulsu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmulu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwsub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwsubu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vxor-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-xsfvcp-x.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
fixed-vectors-xsfvcp-xv.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
fixed-vectors-xsfvcp-xvv.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
fixed-vectors-xsfvcp-xvw.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
fixed-vectors-zext-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-zext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
float-round-conv.ll
[RISCV] Make performFP_TO_INTCombine fold with ISD::FRINT. (#76020)
2023-12-21 15:03:36 +08:00
floor-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
fmaximum-sdnode.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fminimum-sdnode.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fnearbyint-constrained-sdnode.ll
…
fnearbyint-sdnode.ll
…
fold-binary-reduce.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fold-scalar-load-crash.ll
[MachineLICM] Allow hoisting loads from invariant address (#70796)
2023-11-16 11:12:10 +00:00
fold-vector-cmp.ll
[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
2023-11-17 12:02:58 -08:00
fold-vp-fadd-and-vp-fmul.ll
[DAG] getNode() - remove oneuse limit from (zext (trunc (assertzext x))) -> (assertzext x) fold (REAPPLIED)
2023-09-22 11:01:38 +01:00
fold-vp-fsub-and-vp-fmul.ll
…
fpclamptosat_vec.ll
Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)"
2023-10-10 15:13:57 -07:00
fptosi-sat.ll
…
fptoui-sat.ll
…
frameindex-addr.ll
…
frint-sdnode.ll
…
fround-costrained-sdnode.ll
…
fround-sdnode.ll
…
froundeven-constrained-sdnode.ll
…
froundeven-sdnode.ll
…
fshr-fshl-vp.ll
[RISCV] default enable splitting regalloc between RVV and other (#72950)
2023-11-30 21:12:46 -06:00
fshr-fshl.ll
…
ftrunc-constrained-sdnode.ll
…
ftrunc-sdnode.ll
…
get_vector_length.ll
…
get-vlen-debugloc.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
half-round-conv.ll
[RISCV] Make performFP_TO_INTCombine fold with ISD::FRINT. (#76020)
2023-12-21 15:03:36 +08:00
handle-noreg-with-implicit-def.mir
[RISCV] Make InitUndef handle undef operand (#65755)
2023-12-01 01:04:42 -06:00
implicit-def-copy.ll
…
inline-asm.ll
…
insert-subvector.ll
[DAG] Fix a miscompile in insert_subvector undef (insert_subvector undef, ..), idx combine (#73587)
2023-11-27 16:45:29 -08:00
insertelt-fp.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-i1.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-int-rv32.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-int-rv64.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
interleave-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
large-rvv-stack-size.mir
…
legalize-load-sdnode.ll
…
legalize-scalable-vectortype.ll
…
legalize-store-sdnode.ll
…
llrint-sdnode.ll
CodeGen/RISCV: increase test coverage of lrint, llrint (#70826)
2023-10-31 19:16:39 +00:00
load-add-store.ll
[RISCV] Precommit test coverage for VLMAX encodable via vsetivli
2023-12-14 09:42:54 -08:00
load-mask.ll
…
localvar.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
lrint-sdnode.ll
CodeGen/RISCV: increase test coverage of lrint, llrint (#70826)
2023-10-31 19:16:39 +00:00
marith-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
mask-exts-truncs-rv32.ll
…
mask-exts-truncs-rv64.ll
…
mask-reg-alloc.mir
[RISCV] Fix using undefined variable %pt2 in mask-reg-alloc.mir testcase (#70764)
2023-11-07 17:05:03 +08:00
masked-load-fp.ll
…
masked-load-int.ll
…
masked-store-fp.ll
…
masked-store-int.ll
…
masked-tama.ll
…
masked-tamu.ll
…
masked-tuma.ll
…
masked-tumu.ll
…
masked-vslide1down-rv32.ll
…
memcpy-inline.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
memory-args.ll
…
memset-inline.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
mgather-sdnode.ll
…
mscatter-combine.ll
[RISCV] Add a combine to form masked.store from unit strided store
2023-09-19 07:45:35 -07:00
mscatter-sdnode.ll
…
mutate-prior-vsetvli-avl.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
named-vector-shuffle-reverse.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
narrow-shift-extend.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
nearbyint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
no-reserved-frame.ll
…
pass-fast-math-flags-sdnode.ll
…
pr52475.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
pr61561.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
pr63459.ll
…
pr63596.ll
…
pr64588.ll
…
reg-alloc-reserve-bp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
reg-coalescing.mir
…
regalloc-fast-crash.ll
[RISCV] default enable splitting regalloc between RVV and other (#72950)
2023-11-30 21:12:46 -06:00
rint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
round-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
roundeven-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
roundtozero-vp.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
rv32-spill-vector-csr.ll
…
rv32-spill-vector.ll
…
rv32-spill-zvlsseg.ll
[RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)
2023-12-05 07:55:01 -08:00
rv64-spill-vector-csr.ll
…
rv64-spill-vector.ll
…
rv64-spill-zvlsseg.ll
[RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)
2023-12-05 07:55:01 -08:00
rvv-args-by-mem.ll
…
rvv-framelayout.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
rvv-out-arguments.ll
…
rvv-peephole-vmerge-masked-vops.ll
[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
2023-11-17 07:07:37 -08:00
rvv-peephole-vmerge-to-vmv.mir
[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)
2023-10-30 15:17:00 +00:00
rvv-peephole-vmerge-vops-mir.ll
…
rvv-peephole-vmerge-vops.ll
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
rvv-stack-align.mir
…
rvv-vmerge-to-vmv.ll
…
rvv-vscale.i32.ll
…
rvv-vscale.i64.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
saddo-sdnode.ll
…
scalable-vector-struct.ll
…
scalar-stack-align.ll
…
select-fp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
select-int.ll
…
select-sra.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
setcc-fp-vp.ll
[RISCV] default enable splitting regalloc between RVV and other (#72950)
2023-11-30 21:12:46 -06:00
setcc-fp.ll
[RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866)
2023-09-27 11:00:19 +08:00
setcc-int-vp-mask.ll
…
setcc-int-vp.ll
…
setcc-integer.ll
…
sf_vfnrclip_x_f_qf.ll
[RISCV] Fix wrong lmul for sf_vfnrclip (#76016)
2023-12-21 13:24:26 +08:00
sf_vfnrclip_xu_f_qf.ll
[RISCV] Fix wrong lmul for sf_vfnrclip (#76016)
2023-12-21 13:24:26 +08:00
sf_vfwmacc_4x4x4.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmacc_2x8x2.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmacc_4x8x4.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccsu_2x8x2.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccsu_4x8x4.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccu_2x8x2.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccu_4x8x4.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccus_2x8x2.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
sf_vqmaccus_4x8x4.ll
[RISCV] Add missing lmul info for SiFive extensions (#76006)
2023-12-20 14:42:47 +08:00
shuffle-reverse.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
sink-splat-operands-i1.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
sink-splat-operands.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
smulo-sdnode.ll
…
splat-vector-split-i64-vl-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
splat-vectors.ll
…
splats-with-mixed-vl.ll
…
sshl_sat_vec.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
stack-coloring-scalablevec.mir
…
stepvector.ll
…
strided-load-store-intrinsics.ll
[RISCV] Add a combine to form masked.store from unit strided store
2023-09-19 07:45:35 -07:00
strided-load-store.ll
…
strided-vpload.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
strided-vpstore.ll
[DAGCombiner] Combine vp.strided.store with unit stride to vp.store (#66774)
2023-09-19 16:43:50 +01:00
subregister-undef-early-clobber.mir
…
tail-agnostic-impdef-copy.mir
…
umulo-sdnode.ll
…
unaligned-loads-stores.ll
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
2023-12-01 11:00:59 -08:00
undef-earlyclobber-chain.ll
…
undef-earlyclobber-chain.mir
[RISCV] Make InitUndef handle undef operand (#65755)
2023-12-01 01:04:42 -06:00
undef-vp-ops.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
unmasked-ta.ll
…
unmasked-tu.ll
…
urem-seteq-vec.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ushl_sat_vec.ll
…
vaadd.ll
…
vaaddu.ll
…
vadc.ll
…
vadd-sdnode.ll
…
vadd-vp-mask.ll
…
vadd-vp.ll
…
vadd.ll
…
vaesdf.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaesdm.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaesef.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaesem.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaeskf1.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaeskf2.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vaesz.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vand-sdnode.ll
…
vand-vp.ll
…
vand.ll
…
vandn-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vandn-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vandn.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
variant-cc.ll
…
vasub.ll
…
vasubu.ll
…
vbrev8.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vbrev.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vclmul.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vclmulh.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vclz.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vcompress.ll
…
vcopysign-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vcpop.ll
…
vcpopv.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vctz.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vdiv-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vdiv-vp.ll
…
vdiv.ll
…
vdivu-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vdivu-vp.ll
…
vdivu.ll
…
vec3-setcc-crash.ll
…
vector-deinterleave-fixed.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vector-deinterleave-load.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-deinterleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-interleave-fixed.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vector-interleave-store.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-interleave.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vector-splice.ll
…
vexts-sdnode.ll
…
vfabs-sdnode.ll
…
vfabs-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfadd-sdnode.ll
…
vfadd-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfadd.ll
…
vfclass-sdnode.ll
…
vfclass-vp.ll
…
vfclass.ll
…
vfcmp-constrained-sdnode.ll
[RISCV] Add isCommutable for pseudos without merge operand
2023-08-29 15:51:17 +08:00
vfcmps-constrained-sdnode.ll
…
vfcopysign-sdnode.ll
…
vfcvt-f-x.ll
…
vfcvt-f-xu.ll
…
vfcvt-rtz-x-f.ll
…
vfcvt-rtz-xu-f.ll
…
vfcvt-x-f.ll
…
vfcvt-xu-f.ll
…
vfdiv-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfdiv-sdnode.ll
…
vfdiv-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfdiv.ll
…
vfirst.ll
…
vfma-vp-combine.ll
…
vfma-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmacc-vp.ll
…
vfmacc.ll
…
vfmadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmadd-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmadd.ll
…
vfmax-sdnode.ll
…
vfmax-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmax.ll
…
vfmerge.ll
…
vfmin-sdnode.ll
…
vfmin-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmin.ll
…
vfmsac-vp.ll
…
vfmsac.ll
…
vfmsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmsub-sdnode.ll
[TwoAddressInstruction] Handle physical registers with LiveIntervals (#66784)
2023-10-19 16:26:30 +01:00
vfmsub.ll
…
vfmul-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmul-sdnode.ll
…
vfmul-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmul.ll
…
vfmuladd-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmv.f.s.ll
…
vfmv.s.f.ll
[RISCV] Add isel pattern for int_riscv_vfmv_s_f with scalar FP constant operand.
2023-11-15 10:51:43 -08:00
vfmv.v.f.ll
…
vfncvt-f-f.ll
…
vfncvt-f-x.ll
…
vfncvt-f-xu.ll
…
vfncvt-rod-f-f.ll
…
vfncvt-rtz-x-f.ll
…
vfncvt-rtz-xu-f.ll
…
vfncvt-x-f.ll
…
vfncvt-xu-f.ll
…
vfncvtbf16-f-f.ll
…
vfneg-sdnode.ll
…
vfneg-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfnmacc-vp.ll
…
vfnmacc.ll
…
vfnmadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfnmadd-sdnode.ll
…
vfnmadd.ll
…
vfnmsac-vp.ll
…
vfnmsac.ll
…
vfnmsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfnmsub-sdnode.ll
…
vfnmsub.ll
…
vfpext-constrained-sdnode.ll
…
vfpext-sdnode.ll
…
vfpext-vp.ll
…
vfptoi-constrained-sdnode.ll
…
vfptoi-sdnode.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptosi-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptosi-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptoui-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptoui-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptrunc-constrained-sdnode.ll
[RISCV] Support STRICT_FP_ROUND and STRICT_FP_EXTEND when only have Zvfhmin (#68559)
2023-10-17 10:10:19 +08:00
vfptrunc-sdnode.ll
…
vfptrunc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfrdiv-vp.ll
…
vfrdiv.ll
…
vfrec7.ll
…
vfredmax.ll
…
vfredmin.ll
…
vfredosum.ll
…
vfredusum.ll
…
vfrsqrt7.ll
…
vfrsub-vp.ll
…
vfrsub.ll
…
vfsgnj.ll
…
vfsgnjn.ll
…
vfsgnjx.ll
…
vfslide1down.ll
…
vfslide1up.ll
…
vfsqrt-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfsqrt-sdnode.ll
…
vfsqrt-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfsqrt.ll
…
vfsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfsub-sdnode.ll
…
vfsub-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfsub.ll
…
vfwadd-sdnode.ll
…
vfwadd-vp.ll
…
vfwadd.ll
…
vfwadd.w.ll
…
vfwcvt-f-f.ll
…
vfwcvt-f-x.ll
…
vfwcvt-f-xu.ll
…
vfwcvt-rtz-x-f.ll
…
vfwcvt-rtz-xu-f.ll
…
vfwcvt-x-f.ll
…
vfwcvt-xu-f.ll
…
vfwcvtbf16-f-f.ll
…
vfwmacc-sdnode.ll
…
vfwmacc-vp.ll
…
vfwmacc.ll
…
vfwmaccbf16.ll
…
vfwmsac-vp.ll
…
vfwmsac.ll
…
vfwmul-sdnode.ll
…
vfwmul.ll
…
vfwnmacc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfwnmacc.ll
…
vfwnmsac-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfwnmsac.ll
…
vfwredosum.ll
…
vfwredusum.ll
…
vfwsub-sdnode.ll
…
vfwsub.ll
…
vfwsub.w.ll
…
vghsh.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vgmul.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vid.ll
…
viota.ll
…
vitofp-constrained-sdnode.ll
…
vitofp-sdnode.ll
…
vle_vid-vfcvt.ll
…
vle.ll
…
vleff-vlseg2ff-output.ll
…
vleff.ll
…
vlm.ll
…
vloxei-rv64.ll
…
vloxei.ll
…
vloxseg-rv32.ll
…
vloxseg-rv64.ll
…
vlse.ll
…
vlseg-rv32.ll
…
vlseg-rv64.ll
…
vlsegff-rv32-dead.ll
…
vlsegff-rv32.ll
…
vlsegff-rv64-dead.ll
…
vlsegff-rv64.ll
…
vlsseg-rv32.ll
…
vlsseg-rv64.ll
…
vluxei-rv64.ll
…
vluxei.ll
…
vluxseg-rv32.ll
…
vluxseg-rv64.ll
…
vmacc-vp.ll
…
vmacc.ll
…
vmadc.carry.in.ll
…
vmadc.ll
…
vmadd-sdnode.ll
[RISCV] DAG combine (mul (add x, 1), y) -> vmadd (#71495)
2023-11-21 13:43:34 +08:00
vmadd-vp.ll
[RISCV] Add tests for vmadd for VP intrinsics. NFC (#70042)
2023-10-26 07:59:25 +01:00
vmadd.ll
…
vmand.ll
…
vmandn.ll
…
vmarith-sdnode.ll
…
vmax-sdnode.ll
…
vmax-vp.ll
…
vmax.ll
…
vmaxu-sdnode.ll
…
vmaxu-vp.ll
…
vmaxu.ll
…
vmclr.ll
…
vmerge.ll
…
vmfeq.ll
…
vmfge.ll
…
vmfgt.ll
…
vmfle.ll
…
vmflt.ll
…
vmfne.ll
…
vmin-sdnode.ll
…
vmin-vp.ll
…
vmin.ll
…
vminu-sdnode.ll
…
vminu-vp.ll
…
vminu.ll
…
vmnand.ll
…
vmnor.ll
…
vmor.ll
…
vmorn.ll
…
vmsbc.borrow.in.ll
…
vmsbc.ll
…
vmsbf.ll
…
vmseq.ll
…
vmset.ll
…
vmsge.ll
…
vmsgeu.ll
…
vmsgt.ll
…
vmsgtu.ll
…
vmsif.ll
…
vmsle.ll
…
vmsleu.ll
…
vmslt.ll
…
vmsltu.ll
…
vmsne.ll
…
vmsof.ll
…
vmul-sdnode.ll
…
vmul-vp-mask.ll
…
vmul-vp.ll
…
vmul.ll
…
vmulh-sdnode.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
vmulh.ll
…
vmulhsu.ll
…
vmulhu-sdnode.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
vmulhu.ll
…
vmv-copy.mir
…
vmv.s.x-rv32.ll
[RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (#66659)
2023-10-20 14:19:04 -04:00
vmv.s.x-rv64.ll
[RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (#66659)
2023-10-20 14:19:04 -04:00
vmv.v.v-rv32.ll
…
vmv.v.v-rv64.ll
…
vmv.v.x-rv32.ll
…
vmv.v.x-rv64.ll
…
vmv.x.s-rv32.ll
…
vmv.x.s-rv64.ll
…
vmxnor.ll
…
vmxor.ll
…
vnclip.ll
…
vnclipu.ll
…
vnmsac-vp.ll
…
vnmsac.ll
…
vnmsub-sdnode.ll
[RISCV] DAG combine (mul (add x, 1), y) -> vmadd (#71495)
2023-11-21 13:43:34 +08:00
vnmsub.ll
…
vnsra-sdnode.ll
…
vnsra-vp.ll
…
vnsra.ll
…
vnsrl-sdnode.ll
[DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
2023-08-30 15:22:57 +01:00
vnsrl-vp.ll
…
vnsrl.ll
…
vor-sdnode.ll
…
vor-vp.ll
…
vor.ll
…
vp-reverse-float-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-float.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-int-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-int.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-mask-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-mask.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vpgather-sdnode.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
vpload.ll
…
vpmerge-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vpscatter-sdnode.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
vpstore.ll
…
vredand.ll
…
vredmax.ll
…
vredmaxu.ll
…
vredmin.ll
…
vredminu.ll
…
vredor.ll
…
vredsum.ll
…
vreductions-fp-sdnode.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
vreductions-fp-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vreductions-int-vp.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
vreductions-int.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
vreductions-mask-vp.ll
…
vreductions-mask.ll
…
vredxor.ll
…
vrem-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vrem-vp.ll
…
vrem.ll
…
vremu-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vremu-vp.ll
…
vremu.ll
…
vrev8.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vrgather-rv32.ll
…
vrgather-rv64.ll
…
vrgatherei16-rv32.ll
…
vrgatherei16-rv64.ll
…
vrgatherei16-subreg-liveness.ll
…
vrol-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vrol.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vror-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vror.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vrsub-sdnode.ll
…
vrsub-vp.ll
…
vrsub.ll
…
vsadd-rv32.ll
…
vsadd-rv64.ll
…
vsadd-sdnode.ll
…
vsaddu-rv32.ll
…
vsaddu-rv64.ll
…
vsaddu-sdnode.ll
…
vsbc.ll
…
vscale-power-of-two.ll
…
vse.ll
…
vselect-fp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vselect-int.ll
…
vselect-mask.ll
…
vselect-vp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
vsetvl-ext.ll
…
vsetvli-insert-crossbb.ll
[LSR][TTI][RISCV] Enable terminator folding for RISC-V
2023-11-29 12:04:06 -08:00
vsetvli-insert-crossbb.mir
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
vsetvli-insert.ll
[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
2023-12-15 09:26:57 -08:00
vsetvli-insert.mir
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
vsetvli-intrinsics.ll
…
vsetvli-regression.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
vsetvli-valid-elen-fp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vsext-vp-mask.ll
…
vsext-vp.ll
…
vsext.ll
…
vsha2ch.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsha2cl.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsha2ms.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vshl-sdnode.ll
…
vshl-vp.ll
…
vsitofp-vp-mask.ll
…
vsitofp-vp.ll
…
vslide1down-constant-vl-rv32.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
vslide1down-rv32.ll
…
vslide1down-rv64.ll
…
vslide1up-constant-vl-rv32.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
vslide1up-rv32.ll
…
vslide1up-rv64.ll
…
vslidedown.ll
…
vslideup.ll
…
vsll.ll
…
vsm3c.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsm3me.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsm4k.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsm4r.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vsm.ll
…
vsmul-rv32.ll
…
vsmul-rv64.ll
…
vsoxei-rv64.ll
…
vsoxei.ll
…
vsoxseg-rv32.ll
…
vsoxseg-rv64.ll
…
vsplats-fp.ll
…
vsplats-i1.ll
…
vsplats-i64.ll
…
vsplats-zfa.ll
[RISCV] Mark the Zfa extension as non-experimental (#68113)
2023-10-03 18:16:13 +01:00
vsra-sdnode.ll
[RISCV] Combine trunc (sra sext (x), zext (y)) to sra (x, smin (y, scalarsizeinbits(y) - 1)) (#65728)
2023-09-17 17:11:28 +08:00
vsra-vp.ll
…
vsra.ll
…
vsrl-sdnode.ll
…
vsrl-vp.ll
…
vsrl.ll
…
vsse.ll
…
vsseg-rv32.ll
…
vsseg-rv64.ll
…
vssra-rv32.ll
…
vssra-rv64.ll
…
vssrl-rv32.ll
…
vssrl-rv64.ll
…
vssseg-rv32.ll
…
vssseg-rv64.ll
…
vssub-rv32.ll
…
vssub-rv64.ll
…
vssub-sdnode.ll
…
vssubu-rv32.ll
…
vssubu-rv64.ll
…
vssubu-sdnode.ll
…
vsub-sdnode.ll
…
vsub-vp-mask.ll
…
vsub-vp.ll
…
vsub.ll
…
vsuxei-rv64.ll
…
vsuxei.ll
…
vsuxseg-rv32.ll
…
vsuxseg-rv64.ll
…
vtrunc-vp-mask.ll
…
vtrunc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vtruncs-sdnode.ll
…
vuitofp-vp-mask.ll
…
vuitofp-vp.ll
…
vwadd-sdnode.ll
…
vwadd-vp.ll
…
vwadd.ll
…
vwadd.w.ll
…
vwaddu.ll
…
vwaddu.w.ll
…
vwmacc-sdnode.ll
…
vwmacc-vp.ll
…
vwmacc.ll
…
vwmaccsu-vp.ll
…
vwmaccsu.ll
…
vwmaccu-vp.ll
…
vwmaccu.ll
…
vwmaccus.ll
…
vwmul-sdnode.ll
…
vwmul.ll
…
vwmulsu.ll
…
vwmulu.ll
…
vwredsum.ll
…
vwredsumu.ll
…
vwsll-sdnode.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vwsll-vp.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vwsll.ll
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
vwsub-sdnode.ll
…
vwsub.ll
…
vwsub.w.ll
…
vwsubu.ll
…
vwsubu.w.ll
…
vxor-sdnode.ll
…
vxor-vp.ll
…
vxor.ll
…
vxrm-insert.ll
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
vxrm.mir
…
vzext-vp-mask.ll
…
vzext-vp.ll
…
vzext.ll
…
wrong-chain-fixed-load.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
wrong-stack-offset-for-rvv-object.mir
…
wrong-stack-slot-rv32.mir
…
wrong-stack-slot-rv64.mir
…
xsfvcp-x.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
xsfvcp-xv.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
xsfvcp-xvv.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
xsfvcp-xvw.ll
[RISCV] Convert all floating point vector type operands to integer vector type (#69559)
2023-11-21 23:19:10 +08:00
xtheadvdot-vmaqa.ll
…
xtheadvdot-vmaqasu.ll
…
xtheadvdot-vmaqau.ll
…
xtheadvdot-vmaqaus.ll
…
zve32-types.ll
…
zvlsseg-copy.mir
…
zvlsseg-spill.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
zvlsseg-zero-vl.ll
…